arXiv subjects

Tairan Cheng

Publications and source records attributed to Tairan Cheng.

2 recordsLinked to original sources

arXiv2026

HINT: Toward an Executable Hardware-Intent Representation Layer for LLM-Driven RTL Generation

Generating implementation-quality RTL with large language models (LLMs) remains difficult because direct generation must resolve microarchitecture while simultaneously producing and debugging low-level code. We present HINT, an executable hardware-intent intermediate representation layer between behavioral specifications or executable oracles and RTL. HINT makes RTL-relevant microarchitecture explicit, supports pre-RTL checking, and supplies explicit RTL-lowering obligations. We evaluate HINT using both a minimal single-agent flow and a full staged workflow. Across seven operator cases, the HINT-mediated route, with no post-synthesis QoR refinement, produces contract-compliant synthesizable RTL on 7/7 cases; Direct C2RTL and C2HLSC apply to five cases and succeed on 5/5 and 1/5, respectively. Under matched Design Compiler synthesis, HINT reduces area by 5.0\%--26.2\% relative to five manual RTL implementations and by 8.9\%--86.1\% relative to five accepted Direct C2RTL results. RealBench AES and SDC, together with a Vortex VPU synthesizing to 561.67k~$\mu\mathrm{m}^2$, further demonstrate specification-driven, protocol-rich, memory-rich, and hierarchical designs. In the controlled operator study, the HINT-mediated route shows better observed convergence and avoids the severe implementation-quality degradation seen in several direct-generation results.

cs.AR↗

arXiv2026

CktEvo: Repository-Level RTL Code Benchmark for Design Evolution

Register-Transfer Level (RTL) coding is an iterative, repository-scale process in which Power, Performance, and Area (PPA) emerge from interactions across many files and the downstream toolchain. While large language models (LLMs) have recently been applied to hardware design, most efforts focus on generation or debugging from natural-language prompts, where ambiguity and hallucinations necessitate expert review. A separate line of work begins from formal inputs, yet typically optimizes high-level synthesis or isolated modules and remains decoupled from cross-file dependencies. In this work, we present CktEvo, a benchmark and reference framework for repo-level RTL evolution. Unlike prior benchmarks consisting of isolated snippets, our benchmark targets complete IP cores where PPA emerges from cross-file dependencies. Our benchmark packages several high-quality Verilog repositories from real-world designs. We formalize the task as: given an initial repository, produce edits that preserve functional behavior while improving PPA. We also provide a closed-loop framework that couples LLM-proposed edits with toolchain feedback to enable cross-file modifications and iterative repair at repository scale. Our experiments demonstrate that the reference framework realizes PPA improvements without any human interactions. CktEvo establishes a rigorous and executable foundation for studying LLM-assisted RTL optimization that matters for engineering practice: repository-level, function-preserving, and PPA-driven.

cs.AR↗