arXiv subjects

Tara Peña

Publications and source records attributed to Tara Peña.

13 recordsLinked to original sources

arXiv2026

Deep Learning to Automate Parameter Extraction and Model Fitting of Two-Dimensional Transistors

We present a deep learning approach to extract physical parameters (e.g., mobility, Schottky contact barrier height, defect profiles) of two-dimensional (2D) transistors from electrical measurements, enabling automated parameter extraction and technology computer-aided design (TCAD) fitting. To facilitate this task, we implement a simple data augmentation and pre-training approach by training a secondary neural network to approximate a physics-based device simulator. This method enables high-quality fits after training the neural network on electrical data generated from physics-based simulations of ~500 devices, a factor >40$\times$ fewer than other recent efforts. Consequently, fitting can be achieved by training on physically rigorous TCAD models, including complex geometry, self-consistent transport, and electrostatic effects, and is not limited to computationally inexpensive compact models. We apply our approach to reverse-engineer key parameters from experimental monolayer WS$_2$ transistors, achieving a median coefficient of determination ($R^2$) = 0.99 when fitting measured electrical data. We also demonstrate that this approach generalizes and scales well by reverse-engineering electrical data on high-electron-mobility transistors while fitting 35 parameters simultaneously. To facilitate future research on deep learning approaches for inverse transistor design, we have published our code and sample data sets online.

cs.LG↗

arXiv2026

Scaling Nanoribbon Transistors with Monolayer Transition Metal Dichalcogenides

Nanoscale transistors require aggressive reduction of all channel dimensions: length, width, and thickness. While monolayer two-dimensional semiconductors (2DS) offer ultimate thickness scaling, good performance has largely been achieved only in micrometer-wide channels. Here, we demonstrate both $\it{n}$- and $\it{p}$-type nanoribbon transistors based on monolayer 2DS, fabricated using a multi-patterning process, reaching channel widths and lengths down to 25-30 nm. 'Anchored' contacts improve device yield, while nanoscale imaging, including tip-enhanced photoluminescence, reveals minimal edge degradation. The devices reach on-state currents up to 560, 420, and 130 $μ$A $μ$m$^{-1}$ at 1 V drain-to-source voltage for $\it{n}$-type MoS$_{2}$, WS$_{2}$, and $\it{p}$-type WSe$_{2}$, respectively, integrated with thin high-$κ$ dielectrics. These results surpass prior reports for single-gated nanoribbons, the WS$_{2}$ by over 100 times, even in normally off (enhancement-mode) transistors. Taken together, these findings suggest that top down patterned 2DS nanoribbons are promising building blocks for future nanosheet transistors.

cond-mat.mtrl-sci↗

arXiv2025

Channel-last gate-all-around nanosheet oxide semiconductor transistors

As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor architectures, such as gate-all-around nanosheets, the conventional channel-first process involves depositing dielectrics directly onto the channel. Atomic layer deposition of gate dielectrics on back-end-of-line compatible channel materials, such as amorphous oxide semiconductors, can induce defects or cause structural modifications that degrade electrical performance. While post-deposition annealing can partially repair this damage, it often degrades other device metrics. We report a novel channel-last concept that prevents such damage. Channel-last gate-all-around self-aligned transistors with amorphous oxide-semiconductor channels exhibit high on-state current ($>$ 1 mA/$μ$m) and low subthreshold swing (minimum of 63 mV/dec) without the need for post-deposition processing. This approach offers a general, scalable pathway for transistors with atomic layer deposited channel materials, enabling the future of low-power three-dimensional electronics.

cond-mat.mtrl-sci↗

arXiv2025

Gate Dielectric Engineering with an Ultrathin Silicon-oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories

We demonstrate a gate dielectric engineering approach leveraging an ultrathin, atomic layer deposited (ALD) silicon oxide interfacial layer (SiL) between the amorphous oxide semiconductor (AOS) channel and the high-k gate dielectric. SiL positively shifts the threshold voltage (V$_T$) of AOS transistors, providing at least four distinct $V_T$ levels with a maximum increase of 500 mV. It achieves stable $V_T$ control without significantly degrading critical device parameters such as mobility, on-state current, all while keeping the process temperature below 225 $^{\circ}$C and requiring no additional heat treatment to activate the dipole. Positive-bias temperature instability tests at 85 $^{\circ}$C indicate a significant reduction in negative $V_{T}$ shifts for SiL-integrated devices, highlighting enhanced reliability. Incorporating this SiL gate stack into two-transistor gain-cell (GC) memory maintains a more stable storage node voltage ($V_{SN}$) (reduces $V_{SN}$ drop by 67\%), by limiting unwanted charge losses. SiL-engineered GCs also reach retention times up to 10,000 s at room temperature and reduce standby leakage current by three orders of magnitude relative to baseline device, substantially lowering refresh energy consumption.

cond-mat.mtrl-sci↗

arXiv2025

Strain-induced Moiré Reconstruction and Memorization in Two-Dimensional Materials without Twist

Two-dimensional (2D) materials with a twist between layers exhibit a moiré interference pattern with larger periodicity than any of the constituent layer unit cells. In these systems, a wealth of exotic phases appear that result from moiré-dependent many-body electron correlation effects or non-trivial band topology. One problem with using twist to generate moiré interference has been the difficulty in creating high-quality, uniform, and repeatable samples due to fabrication through mechanical stacking with viscoelastic stamps. Here we show, a new method to generate moiré interference through the controlled application of layer-by-layer strain (heterostrain) on non-twisted 2D materials, where moiré interference results from strain-induced lattice mismatch without twisting or stacking. Heterostrain generation is achieved by depositing stressed thin films onto 2D materials to apply large strains to the top layers while leaving layers further down less strained. We achieve deterministic control of moiré periodicity and symmetry in non-twisted 2D multilayers and bilayers, with 97% yield, through varying stressor film force (film thickness X film stress) and geometry. Moiré reconstruction effects are memorized after the removal of the stressor layers. Control over the strain degree-of-freedom opens the door to a completely unexplored set of unrealized tunable moiré geometric symmetries, which may now be achieved in a high-yield and user-skill independent process taking only hours. This technique solves a long-standing throughput bottleneck in new moiré quantum materials discovery and opens the door to industrially-compatible manufacturing for 2D moiré-based electronic or optical devices.

cond-mat.mtrl-sci↗

arXiv2025

High-current p-type transistors from precursor-engineered synthetic monolayer WSe$_2$

Monolayer tungsten diselenide (WSe$_2$) is a leading candidate for nanoscale complementary logic. However, high defect densities introduced during thin-film growth and device fabrication have limited p-type transistor performance. Here, we report a combined strategy of precursor-engineered chemical vapor deposition and damage-minimizing fabrication to overcome this limitation. By converting tungsten trioxide and residual oxyselenides into reactive suboxides before growth, and precisely regulating selenium delivery during deposition, we synthesize uniform, centimeter-scale monolayer WSe$_2$ films with charged defect densities as low as $5 \times 10^{9}$ cm$^{-2}$. Transistors fabricated from these films achieve record p-type on-state current up to $888 μ$A$\cdotμ$m$^{-1}$ at $V_{\mathrm{DS}}=-1$ V, matching leading n-type devices. This leap in material quality closes the p-type performance gap without exotic doping or contact materials, marking a critical step towards complementary two-dimensional semiconductor circuits.

cond-mat.mtrl-sci↗

arXiv2025

High-field Breakdown and Thermal Characterization of Indium Tin Oxide Transistors

Amorphous oxide semiconductors are gaining interest for logic and memory transistors compatible with low-temperature fabrication. However, their low thermal conductivity and heterogeneous interfaces suggest that their performance may be severely limited by self-heating, especially at higher power and device densities. Here, we investigate the high-field breakdown of ultrathin (~4 nm) amorphous indium tin oxide (ITO) transistors with scanning thermal microscopy (SThM) and multiphysics simulations. The ITO devices break irreversibly at channel temperatures of ~180 °C and ~340 °C on SiO${_2}$ and HfO${_2}$ substrates, respectively, with failure primarily caused by thermally-induced compressive strain near the device contacts. Combining SThM measurements with simulations allows us to estimate a thermal boundary conductance (TBC) of 35 ${\pm}$ 12 MWm${^-}$${^2}$K${^-}$${^1}$ for ITO on SiO${_2}$, and 51 ${\pm}$ 14 MWm${^-}$${^2}$K${^-}$${^1}$ for ITO on HfO${_2}$. The latter also enables significantly higher breakdown power due to better heat dissipation and closer thermal expansion matching. These findings provide insights into the thermo-mechanical limitations of indium-based amorphous oxide transistors, which are important for more reliable and high-performance logic and memory applications.

physics.app-ph↗

arXiv2024

Direct X-Ray Measurements of Strain in Monolayer MoS$_{2}$ from Capping Layers and Geometrical Features

Strain induced through fabrication, both by patterning and capping, can be used to change the properties of two-dimensional (2D) materials or other thin films. Here, we explore how capping layers impart strain to monolayer MoS$_{2}$ using direct x-ray diffraction measurements of the lattice. We first observe the impact of naturally-oxidized metal layers ($\sim$1.5 nm Al) and subsequently-deposited Al$_{2}$O$_{3}$ (15 nm to 25 nm thick) on the 2D material, and find that the strain imparted to MoS$_{2}$ is mainly controlled by the interfacial adhesion of the seed layer in addition to the substrate adhesion. Then, using test structures which mimic transistor contacts, we measure enhanced strain from such patterns compared to blanket films. Furthermore, we observe significant tensile strain - up to 2% in monolayer MoS$_{2}$, one of the largest experimental values to date on a rigid substrate - due to highly-stressed blanket metal capping layers. These results provide direct evidence supporting previous reports of strain effects in 2D material devices.

cond-mat.mtrl-sci↗

arXiv2023

An atomistic insight into moiré reconstruction in Twisted Bilayer Graphene beyond the magic angle

Twisted bilayer graphene exhibits electronic properties that are highly correlated with the size and arrangement of moiré patterns. While rigid rotation of two layers creates the topology of moiré patterns, local rearrangements of the atoms due to interlayer van der Waals interactions result in atomic reconstruction within the moiré cells. The ability to manipulate these patterns by controlling twist angle and/or externally applied strain provides a promising route to tune their properties. While this phenomenon has been extensively studied for angles close to or smaller than the magic angle (θm=1.1°), its extent for higher angles and how it evolves with strain is unknown and is believed to be mostly absent at high angles. We use theoretical and numerical analyses to resolve reconstruction in angles above θm using interpretive and fundamental physical measures. In addition, we propose a method to identify local regions within moiré cells and track their evolution with strain for a range of representative high twist angles. Our results show that reconstruction is actively present beyond the magic angle and its contribution to the evolution of the moiré cells is major. Our theoretical method to correlate local and global phonon behavior provides further validation on the role of reconstruction at higher angles. Our findings provide a better understanding of moiré reconstruction in large twist angles and the evolution of moiré cells in the presence of strain, that might be very crucial for twistronics-based applications.

cond-mat.mtrl-sci↗

arXiv2023

Moiré Engineering in 2D Heterostructures with Process-Induced Strain

We report deterministic control over moiré superlattice interference pattern in twisted bilayer graphene by implementing designable device-level heterostrain with process-induced strain engineering, a widely used technique in industrial silicon nanofabrication processes. By depositing stressed thin films onto our twisted bilayer graphene samples, heterostrain magnitude and strain directionality can be controlled by stressor film force (film stress x film thickness) and patterned stressor geometry, respectively. We examine strain and moiré interference with Raman spectroscopy through in-plane and moiré-activated phonon mode shifts. Results support systematic C$_{3}$ rotational symmetry breaking and tunable periodicity in moiré superlattices under the application of uniaxial or biaxial heterostrain. Experimental results are validated by molecular statics simulations and density functional theory based first principles calculations. This provides a method to not only tune moiré interference without additional twisting, but also allows for a systematic pathway to explore different van der Waals based moiré superlattice symmetries by deterministic design.

cond-mat.mes-hall↗

arXiv2022

Ultrasonic Delamination Based Adhesion Testing for High-Throughput Assembly of van der Waals Heterostructures

Two-dimensional (2D) materials assembled into van der Waals (vdW) heterostructures contain unlimited combinations of mechanical, optical, and electrical properties that can be harnessed for potential device applications. Critically, these structures require control over interfacial adhesion in order for them to be constructed and to have enough integrity to survive industrial fabrication processes upon their integration. Here, we promptly determine the quality of adhesion of various exfoliated 2D materials on conventional SiO$_{2}$/Si substrates using ultrasonic delamination threshold testing. This test allows us to quickly infer relative substrate adhesion based on the percent area of 2D flakes that survive a fixed time in an ultrasonic bath, allowing for control over process parameters that yield high or poor adhesion. We leverage this control of adhesion to optimize the vdW heterostructure assembly process, where we show that samples with high or low substrate adhesion relative to each other can be used selectively to construct high-throughput vdW stacks. Instead of tuning the adhesion of polymer stamps to 2D materials with constant 2D-substrate adhesion, we tune the 2D-substrate adhesion with constant stamp adhesion to 2D materials. The polymer stamps may be reused without any polymer melting steps, thus avoiding high temperatures (<120°C) and allowing for high-throughput production. We show that this procedure can be used to create high-quality 2D twisted bilayer graphene on SiO$_{2}$/Si, characterized with atomic force microscopy and Raman spectroscopic mapping, as well as low-angle twisted bilayer WSe$_{2}$ on h-BN/SiO$_{2}$/Si, where we show direct real-space visualization of moiré reconstruction with tilt angle-dependent scanning electron microscopy.

physics.app-ph↗

arXiv2021

Strain Engineering 2D MoS$_{2}$ with Thin Film Stress Capping Layers

We demonstrate a method to induce tensile and compressive strain into two-dimensional transition metal dichalcogenide (TMDC) MoS$_{2}$ via the deposition of stressed thin films to encapsulate exfoliated flakes. With this technique we can directly engineer MoS$_{2}$ strain magnitude by changing deposited thin film stress, therefore allowing variable strain to be applied on a flake-to-flake level. These thin film stressors are analogous to SiN$_{x}$ based stressors implemented in industrial CMOS processes to enhance Si mobility, suggesting that our concept is highly scalable and may be applied for large-scale integration of strain engineered TMDC devices. We choose optically transparent stressors to allow us to probe MoS$_{2}$ strain through Raman spectroscopy. Combining thickness dependent analyses of Raman peak shifts in MoS$_{2}$ with atomistic simulations, we can explore layer-by-layer strain transfer. MoS$_{2}$ on conventional substrates (SiO$_{2}$, MgO) show strain transfer into the top two layers of multilayer flakes with limited strain transfer to monolayers due to substrate adhesion. To mitigate this limitation, we also explore stressors on van der Waals heterostructures constructed of monolayer (1L) MoS$_{2}$ on hexagonal boron nitride (h-BN). This concept frees the 1L-MoS$_{2}$ allowing for a 0.85$\%$ strain to be applied to the monolayer with a corresponding strain induced bandgap change of 75 meV. By using thin films with higher stress, strain may be engineered to be even higher. Various stressors and deposition methods are considered, showing a stressor material independent transfer of strain that only depends on stressor film force with negligible defects induced into MoS$_{2}$ when thermal evaporation is used.

cond-mat.mes-hall↗

arXiv2019

Strain-Based Room-Temperature Non-Volatile MoTe$_2$ Ferroelectric Phase Change Transistor

The primary mechanism of operation of almost all transistors today relies on electric-field effect in a semiconducting channel to tune its conductivity from the conducting 'on'-state to a non-conducting 'off'-state. As transistors continue to scale down to increase computational performance, physical limitations from nanoscale field-effect operation begin to cause undesirable current leakage that is detrimental to the continued advancement of computing. Using a fundamentally different mechanism of operation, we show that through nanoscale strain engineering with thin films and ferroelectrics (FEs) the transition metal dichalcogenide (TMDC) MoTe$_2$ can be reversibly switched with electric-field induced strain between the 1T'-MoTe$_2$ (semimetallic) phase to a semiconducting MoTe$_2$ phase in a field effect transistor geometry. This alternative mechanism for transistor switching sidesteps all the static and dynamic power consumption problems in conventional field-effect transistors (FETs). Using strain, we achieve large non-volatile changes in channel conductivity (G$_{on}$/G$_{off}$~10$^7$ vs. G$_{on}$/G$_{off}$~0.04 in the control device) at room temperature. Ferroelectric devices offer the potential to reach sub-ns nonvolatile strain switching at the attojoule/bit level, having immediate applications in ultra-fast low-power non-volatile logic and memory while also transforming the landscape of computational architectures since conventional power, speed, and volatility considerations for microelectronics may no longer exist.

physics.app-ph↗