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Tarek El-Ghazawi

Publications and source records attributed to Tarek El-Ghazawi.

At least 19 recordsLinked to original sources

QoS-Efficient Serving of Multiple Mixture-of-Expert LLMs Using Partial Runtime Reconfiguration

The deployment of mixture-of-experts (MoE) large language models (LLMs) presents significant challenges due to their high memory demands. These challenges become even more pronounced in multi-tenant environments, where shared resources must accommodate multiple models, limiting the effectiveness of conventional virtualization techniques. This paper addresses the problem of efficiently serving multiple fine-tuned MoE-LLMs on a single-GPU. We propose a serving system that employs \textit{similarity-based expert consolidation} to reduce the overall memory footprint by sharing similar experts across models. To ensure output quality, we introduce \textit{runtime partial reconfiguration}, dynamically replacing non-expert layers when processing requests from different models. As a result, our approach achieves a competitive output quality while maintaining throughput comparable to serving a single model while incurring a negligible increase in time-to-first-token (TTFT). Experiments on a server with a single NVIDIA A100 GPU (80GB) using Mixtral-8x7B models demonstrate an 85\% average reduction in turnaround time compared to NVIDIA's multi-instance GPU (MIG). Furthermore, experiments on Google's Switch Transformer Base-8 model with up to four variants demonstrate the scalability and resilience of our approach in maintaining output quality compared to other model merging baselines, highlighting its effectiveness.

cs.LG

Mixture of Experts with Mixture of Precisions for Tuning Quality of Service

The increasing demand for deploying large Mixture-of-Experts (MoE) models in resource-constrained environments necessitates efficient approaches to address their high memory and computational requirements challenges. Moreover, given that tasks come in different user-defined constraints and the available resources change over time in multi-tenant environments, it is necessary to design an approach which provides a flexible configuration space. This paper presents an adaptive serving approach for the efficient deployment of MoE models, capitalizing on partial quantization of the experts. By dynamically determining the number of quantized experts and their distribution across CPU and GPU, our approach explores the Pareto frontier and offers a fine-grained range of configurations for tuning throughput and model quality. Our evaluation on an NVIDIA A100 GPU using a Mixtral 8x7B MoE model for three language modelling benchmarks demonstrates that the throughput of token generation can be adjusted from 0.63 to 13.00 token per second. This enhancement comes with a marginal perplexity increase of 3.81 to 4.00, 13.59 to 14.17, and 7.24 to 7.40 for WikiText2, PTB, and C4 datasets respectively under maximum quantization. These results highlight the practical applicability of our approach in dynamic and accuracy-sensitive applications where both memory usage and output quality are important.

cs.DC

Online Service Migration in Mobile Edge with Incomplete System Information: A Deep Recurrent Actor-Critic Learning Approach

Multi-access Edge Computing (MEC) is an emerging computing paradigm that extends cloud computing to the network edge to support resource-intensive applications on mobile devices. As a crucial problem in MEC, service migration needs to decide how to migrate user services for maintaining the Quality-of-Service when users roam between MEC servers with limited coverage and capacity. However, finding an optimal migration policy is intractable due to the dynamic MEC environment and user mobility. Many existing studies make centralized migration decisions based on complete system-level information, which is time-consuming and also lacks desirable scalability. To address these challenges, we propose a novel learning-driven method, which is user-centric and can make effective online migration decisions by utilizing incomplete system-level information. Specifically, the service migration problem is modeled as a Partially Observable Markov Decision Process (POMDP). To solve the POMDP, we design a new encoder network that combines a Long Short-Term Memory (LSTM) and an embedding matrix for effective extraction of hidden information, and further propose a tailored off-policy actor-critic algorithm for efficient training. The extensive experimental results based on real-world mobility traces demonstrate that this new method consistently outperforms both the heuristic and state-of-the-art learning-driven algorithms and can achieve near-optimal results on various MEC scenarios.

cs.NI

Reconfigurable Application-Specific Photonic Integrated Circuit for solving Partial Differential Equations

Solving mathematical equations faster and more efficiently has been a Holy Grail for centuries for scientists and engineers across all disciplines. While electronic digital circuits have revolutionized equation solving in recent decades, it has become apparent that performance gains from brute-force approaches of compute-solvers are quickly saturating over time. Instead, paradigms that leverage the universes natural tendency to minimize a systems free energy, such as annealers or Ising Machines, are being sought after due to favorable complexity scaling. Here we introduce a programmable analog solver leveraging the mathematical formal equivalence between Maxwells equations and photonic circuitry. It features a mesh network of nanophotonic beams to find solutions to partial differential equations. As an example, we designed, fabricated, and demonstrated a novel application-specific photonic integrated circuit comprised of electro-optically reconfigurable nodes, and experimentally validated 90% accuracy with respect to a commercial solver. Finally, we tested this photonic integrated chip performance by simulating thermal diffusion on a spacecrafts heat shield during re-entry to a planets atmosphere. The programmable light-circuitry presented herein offers a facile route for solving complex problems and thus will have profound potential applications across many scientific and engineering fields.

physics.optics

Analog Computing with Metatronic Circuits

Analog photonic solutions offer unique opportunities to address complex computational tasks with unprecedented performance in terms of energy dissipation and speeds, overcoming current limitations of modern computing architectures based on electron flows and digital approaches. The lack of modularization and lumped element reconfigurability in photonics has prevented the transition to an all-optical analog computing platform. Here, we explore a nanophotonic platform based on epsilon-near-zero materials capable of solving in the analog domain partial differential equations (PDE). Wavelength stretching in zero-index media enables highly nonlocal interactions within the board based on the conduction of electric displacement, which can be monitored to extract the solution of a broad class of PDE problems. By exploiting control of deposition technique through process parameters, we demonstrate the possibility of implementing the proposed nano-optic processor using CMOS-compatible indium-tin-oxide, whose optical properties can be tuned by carrier injection to obtain programmability at high speeds and low energy requirements. Our nano-optical analog processor can be integrated at chip-scale, processing arbitrary inputs at the speed of light.

physics.optics

A Design Methodology for Post-Moore's Law Accelerators: The Case of a Photonic Neuromorphic Processor

Over the past decade alternative technologies have gained momentum as conventional digital electronics continue to approach their limitations, due to the end of Moore's Law and Dennard Scaling. At the same time, we are facing new application challenges such as those due to the enormous increase in data. The attention, has therefore, shifted from homogeneous computing to specialized heterogeneous solutions. As an example, brain-inspired computing has re-emerged as a viable solution for many applications. Such new processors, however, have widened the abstraction gamut from device level to applications. Therefore, efficient abstractions that can provide vertical design-flow tools for such technologies became critical. Photonics in general, and neuromorphic photonics in particular, are among the promising alternatives to electronics. While the arsenal of device level toolbox for photonics, and high-level neural network platforms are rapidly expanding, there has not been much work to bridge this gap. Here, we present a design methodology to mitigate this problem by extending high-level hardware-agnostic neural network design tools with functional and performance models of photonic components. In this paper we detail this tool and methodology by using design examples and associated results. We show that adopting this approach enables designers to efficiently navigate the design space and devise hardware-aware systems with alternative technologies.

cs.ET

OE-CAM: A Hybrid Opto-Electronic Content Addressable Memory

A content addressable memory (CAM) is a type of memory that implements a parallel search engine at its core. A CAM takes as an input a value and outputs the address where this value is stored in case of a match. CAMs are used in a wide range of applications including networking, cashing, neuromorphic associative memories, multimedia, and data analytics. Here, we introduce a novel opto-electronic CAM (OE-CAM) utilizing the integrated silicon photonic platform. In our approach, we explore the performance of an experimental OE-CAM and verify the efficiency of the device at 25Gbit/s while maintaining the bit integrity under noise conditions. We show that OE-CAM enables a) two orders of magnitude faster search functionality resulting in b) a five orders of magnitude lower power-delay-product compared to CAMs implementations based on other emerging technologies. This remarkable performance potential is achieved by utilizing i) a high parallelism of wavelength-division-multiplexing in the optical domain, combined with ii) 10s of GHz-fast opto-electronic components, packaged in iii) integrated photonics for 10-100s ps-short communication delays. We further verify the upper optical input power limit of this OE-CAM to be given by parasitic nonlinearities inside the silicon waveguides, and the minimal detectable optical power at the back-end photoreceivers responsivity given channel noise. Such energy-efficient and short-delay OE-CAMs could become a key component of functional photonic-augmented ASICS, co-processors, or smart sensors.

physics.app-ph

A Winograd-based Integrated Photonics Accelerator for Convolutional Neural Networks

Neural Networks (NNs) have become the mainstream technology in the artificial intelligence (AI) renaissance over the past decade. Among different types of neural networks, convolutional neural networks (CNNs) have been widely adopted as they have achieved leading results in many fields such as computer vision and speech recognition. This success in part is due to the widespread availability of capable underlying hardware platforms. Applications have always been a driving factor for design of such hardware architectures. Hardware specialization can expose us to novel architectural solutions, which can outperform general purpose computers for tasks at hand. Although different applications demand for different performance measures, they all share speed and energy efficiency as high priorities. Meanwhile, photonics processing has seen a resurgence due to its inherited high speed and low power nature. Here, we investigate the potential of using photonics in CNNs by proposing a CNN accelerator design based on Winograd filtering algorithm. Our evaluation results show that while a photonic accelerator can compete with current-state-of-the-art electronic platforms in terms of both speed and power, it has the potential to improve the energy efficiency by up to three orders of magnitude.

cs.ET

ITO-based Electro-absorption Modulator for Photonic Neural Activation Function

Recently integrated optics has become an intriguing platform for implementing machine learning algorithms and inparticular neural networks. Integrated photonic circuits can straightforwardly perform vector-matrix multiplicationswith high efficiency and low power consumption by using weighting mechanism through linear optics. Although,this can not be said for the activation function which requires either nonlinear optics or an electro-optic module withan appropriate dynamic range. Even though all-optical nonlinear optics is potentially faster, its current integrationis challenging and is rather inefficient. Here we demonstrate an electro-absorption modulator based on an IndiumTin Oxide layer, whose dynamic range is used as nonlinear activation function of a photonic neuron. The nonlinearactivation mechanism is based on a photodiode, which integrates the weighed products, and whose photovoltage drivesthe elecro-absorption modulator. The synapse and neuron circuit is then constructed to execute a 200-node MNISTclassification neural network used for benchmarking the nonlinear activation function and compared with an equivalentelectronic module.

physics.app-ph

Energy-Quality Scaling in Analog Mesh Computers

The recent push for post-Moore computer architectures has introduced a wide variety of application-specific accelerators. One particular accelerator, the resistance network analogue, has been well received due to its ability to efficiently solve partial differential equations by eliminating the iterative stages required by today's numerical solvers. However, in the ago of programmable integrated circuits, the static nature of the resistance network analogue, and other analog mesh computers like it, has relegated it to an academic curiosity. Recent developments in materials, such as the memristor, have made the resistance network analogue viable for inclusion in future heterogeneous computer architectures. However, selection of an appropriate sized mesh to be incorporated into a computer system requires that energy-quality trade-offs are made regarding the problem size and required resolution of the solution. This paper provides an in-depth study of the scaling of analog mesh computer hardware, from the perspective of energy per bit and required resolution, introduces a metric to aid in quantifying analog mesh computers with different parameters, and introduces a method of virtualization which enables an analog mesh computer of a fixed size to approximate the calculations of a larger-sized mesh.

cs.ET

Adaptive Mesh Refinement in Analog Mesh Computers

The call for efficient computer architectures has introduced a variety of application-specific compute engines to the heterogeneous computing landscape. One particular engine, the analog mesh computer, has been well received due to its ability to efficiently solve partial differential equations by eliminating the iterative stages common to numerical solvers. This article introduces an implementation of refinement for analog mesh computers.

math.NA

Neuromorphic photonics with electro-absorption modulators

Photonic neural networks benefit from both the high channel capacity- and the wave nature of light acting as an effective weighting mechanism through linear optics. The neuron's activation function, however, requires nonlinearity which can be achieved either through nonlinear optics or electro-optics. Nonlinear optics, while potentially faster, is challenging at low optical power. With electro-optics, a photodiode integrating the weighted products of a photonic perceptron can be paired directly to a modulator, which creates a nonlinear transfer function for efficient operating. Here we model the activation functions of five types of electro-absorption modulators, analyze their individual performance over varying performance parameters, and simulate their combined effect on the inference of the neural network

physics.app-ph

PCNNA: A Photonic Convolutional Neural Network Accelerator

Convolutional Neural Networks (CNN) have been the centerpiece of many applications including but not limited to computer vision, speech processing, and Natural Language Processing (NLP). However, the computationally expensive convolution operations impose many challenges to the performance and scalability of CNNs. In parallel, photonic systems, which are traditionally employed for data communication, have enjoyed recent popularity for data processing due to their high bandwidth, low power consumption, and reconfigurability. Here we propose a Photonic Convolutional Neural Network Accelerator (PCNNA) as a proof of concept design to speedup the convolution operation for CNNs. Our design is based on the recently introduced silicon photonic microring weight banks, which use broadcast-and-weight protocol to perform Multiply And Accumulate (MAC) operation and move data through layers of a neural network. Here, we aim to exploit the synergy between the inherent parallelism of photonics in the form of Wavelength Division Multiplexing (WDM) and sparsity of connections between input feature maps and kernels in CNNs. While our full system design offers up to more than 3 orders of magnitude speedup in execution time, its optical core potentially offers more than 5 order of magnitude speedup compared to state-of-the-art electronic counterparts.

cs.ET

Integrated Nanophotonics Architecture for Residue Number System Arithmetic

Residue number system (RNS) enables dimensionality reduction of an arithmetic problem by representing a large number as a set of smaller integers, where the number is decomposed by prime number factorization using the moduli as basic functions. These reduced problem sets can then be processed independently and in parallel, thus improving computational efficiency and speed. Here we show an optical RNS hardware representation based on integrated nanophotonics. The digit-wise shifting in RNS arithmetic is expressed as spatial routing of an optical signal in 2x2 hybrid photonic-plasmonic switches. Here the residue is represented by spatially shifting the input waveguides relative to the routers outputs, where the moduli are represented by the number of waveguides. By cascading the photonic 2x2 switches, we design a photonic RNS adder and a multiplier forming an all-to-all sparse directional network. The advantage of this photonic arithmetic processor is the short (10's ps) computational execution time given by the optical propagation delay through the integrated nanophotonic router. Furthermore, we show how photonic processing in-the-network leverages the natural parallelism of optics such as wavelength-division-multiplexing or optical angular momentum in this RNS processor. A key application for photonic RNS is the functional analysis convolution with widespread usage in numerical linear algebra, computer vision, language- image- and signal processing, and neural networks.

cs.ET

Hybrid Photonic-Plasmonic Non-blocking Broadband 5x5 Router for Optical Networks

Photonic data routing in optical networks overcomes the limitations of electronic routers with respect to data rate, latency, and energy consumption while suffering from dynamic power consumption, non-simultaneous usage of multiple wavelength channels, and large footprints. Here we show the first hybrid photonic-plasmonic, non-blocking, broadband 5x5 router. The compact footprint (<250 μm2) enables high operation speed (480 GHz) requiring only 82 fJ/bit (1.9 dB) of averaged energy consumption (routing loss). The router supports multi-wavelength up to 206 nm in the telecom band. Having a data-capacity of >70 Tbps, thus demonstrating key features required by future high data-throughput optical networks.

physics.app-ph

MODetector (MOD): A Dual-Functional Optical Modulator-Detector for On-Chip Communication

Physical challenges at the device and interconnect level limit both network and computing energy efficiency. While photonics is being considered to address interconnect bottlenecks, optical routing is still limited by electronic circuitry, requiring substantial overhead for optical-electrical-optical conversion. Here we show a novel design of an integrated broadband photonic-plasmonic hybrid device termed MODetector featuring dual light modulation and detection function to act as an optical transceiver in the photonic network-on-chip. With over 10 dB extinction ratio and 0.8 dB insertion loss at the modulation state, this MODetector provides 0.7 W/A responsivity in the detection state with 36 ps response time. This multi-functional device: (i) eliminates OEO conversion, (ii) reduces optical losses from photodetectors when not needed, and (iii) enables cognitive routing strategies for network-on-chips.

physics.app-ph

D3NOC: Dynamic Data-Driven Network On Chip in Photonic Electronic Hybrids

In this paper, we present a reconfigurable hybrid Photonic-Plasmonic Network-on-Chip (NoC) based on the Dynamic Data Driven Application System (DDDAS) paradigm. In DDDAS computations and measurements form a dynamic closed feedback loop in which they tune one another in response to changes in the environment. Our proposed system enables dynamic augmentation of a base electrical mesh topology with an optical express bus during the run-time. In addition, the measurement process itself adjusts to the environment. In order to achieve lower latencies, lower dynamic power, and higher throughput, we take advantage of a Configurable Hybrid Photonic Plasmonic Interconnect (CHyPPI) for our reconfigurable connections. We evaluate the performance and power of our system against kernels from NAS Parallel Benchmark (NPB) in addition to some synthetically generated traffic. In comparison to a 16x16 base electrical mesh, D3NOC shows up to 89% latency and 67% dynamic power net improvements beyond overhead-corrected performance. It should be noted that the design-space of NoC reconfiguration is vast and the goal of this study is not design-space exploration. Our goal is to show the potentials of adaptive dynamic measurements when coupled with other reconfiguration techniques in the NoC context.

cs.OH

MorphoNoC: Exploring the Design Space of a Configurable Hybrid NoC using Nanophotonics

As diminishing feature sizes drive down the energy for computations, the power budget for on-chip communication is steadily rising. Furthermore, the increasing number of cores is placing a huge performance burden on the network-on-chip (NoC) infrastructure. While NoCs are designed as regular architectures that allow scaling to hundreds of cores, the lack of a flexible topology gives rise to higher latencies, lower throughput, and increased energy costs. In this paper, we explore MorphoNoCs - scalable, configurable, hybrid NoCs obtained by extending regular electrical networks with configurable nanophotonic links. In order to design MorphoNoCs, we first carry out a detailed study of the design space for Multi-Write Multi-Read (MWMR) nanophotonics links. After identifying optimum design points, we then discuss the router architecture for deploying them in hybrid electronic-photonic NoCs. We then study explore the design space at the network level, by varying the waveguide lengths and the number of hybrid routers. This affords us to carry out energy-latency trade-offs. For our evaluations, we adopt traces from synthetic benchmarks as well as the NAS Parallel Benchmark suite. Our results indicate that MorphoNoCs can achieve latency improvements of up to 3.0x or energy improvements of up to 1.37x over the base electronic network.

cs.OH