arXiv subjects

Tasnuva Farheen

Publications and source records attributed to Tasnuva Farheen.

12 recordsLinked to original sources

arXiv2026

Adaptive Error Budget Allocation for Fault-Tolerant Quantum Resource Estimation: A Metaheuristic Approach

System-level resource estimation is a key component of fault-tolerant quantum computing (FTQC) toolchains. Its efficiency depends on how global error tolerance is allocated across logical operations, T-state distillation, and rotation synthesis to minimize physical resource overhead. The commonly used uniform-allocation strategy ignores circuit-specific structure and can overprovision inactive or less critical subsystems, leading to inflated space-time estimates. Prior work aims to address this limitation using supervised models trained on offline-generated datasets. However, this approach incurs additional data-generation costs and limits deployment flexibility. To overcome these drawbacks, we propose a training-free optimization framework that performs derivative-free search directly on the Azure Quantum Resource Estimator (AQRE), enabling instance-specific error budget allocation for previously unseen circuits without requiring offline training data. To evaluate robustness to optimizer choice, we instantiate the framework with two structurally distinct metaheuristics, simulated annealing and quantum particle swarm optimization. We evaluate our framework across 433 circuits spanning 2 to 91 qubits from 31 families in the MQT Bench suite. Across the benchmark suite, both methods reduce space-time cost by more than 33\% on average and agree within 1.34\% points, indicating that the gains are stable across different metaheuristic search strategies. Our analysis further finds that the optimization benefit is driven primarily by error-profile asymmetry rather than circuit scale, and the metric, Gini coefficient of optimized allocation, provides an interpretable diagnostic of expected improvement. Together, these results position adaptive error budget allocation as a system-software optimization layer for FTQC resource estimation pipeline.

quant-ph↗

arXiv2026

A Game Theoretic Approach for Optimizing Quantum Error Budget Distribution

Current fault-tolerant quantum compilers allocate error budgets uniformly during resource estimation, causing suboptimal physical resource overhead. We optimize this allocation using a potential game formulation, where Nash Equilibrium yields a Pareto-optimal distribution across logical operations, T-state distillation, and rotation synthesis. An iterated best response (IBR) algorithm converges to this equilibrium through monotonic descent of the shared cost function. Evaluation across 433 MQT benchmarks demonstrates an average reduction of 30.22\% in physical resource requirements relative to uniform baselines, with peak improvements of 97.81\% for specific circuit instances. This establishes a game-theoretic foundation for strategic error budget optimization in fault-tolerant quantum design automation.

quant-ph↗

arXiv2026

InterPUF: Distributed Authentication via Physically Unclonable Functions and Multi-party Computation for Reconfigurable Interposers

Modern system-in-package (SiP) platforms increasingly adopt reconfigurable interposers to enable plug-and-play chiplet integration across heterogeneous multi-vendor ecosystems. However, this flexibility introduces severe trust challenges, as traditional authentication schemes fail to scale or adapt in decentralized, post-fabrication programmable environments. This paper presents InterPUF, a compact and scalable authentication framework that transforms the interposer into a distributed root of trust. InterPUF embeds a route-based differential delay physically unclonable function (PUF) across the reconfigurable interconnect and secures authentication using multi-party computation (MPC), ensuring raw PUF signatures are never exposed. Our hardware evaluation shows only 0.23% area and 0.072% power overhead across diverse chiplets while preserving authentication latency within tens of nanoseconds. Simulation results using pyPUF confirm strong uniqueness, reliability, and modeling resistance under process, voltage, and temperature variations. By combining interposer-resident PUF primitives with cryptographic hashing and collaborative verification, InterPUF enforces a minimal-trust authentication model without relying on a centralized anchor.

cs.CR↗

arXiv2025

Pulse-to-Circuit Characterization of Stealthy Crosstalk Attack on Multi-Tenant Superconducting Quantum Hardware

Hardware crosstalk in multi-tenant superconducting quantum computers constitutes a significant security threat, enabling adversaries to inject targeted errors across tenant boundaries. We present the first end-to-end framework for mapping physical pulse-level attacks to interpretable logical error channels, integrating density-matrix simulation, quantum process tomography (QPT), and a novel isometry-based circuit extraction method. Our pipeline reconstructs the complete induced error channel and fits an effective logical circuit model, revealing a fundamentally asymmetric attack mechanism: one adversarial qubit acts as a driver to set the induced logical rotation, while a second, the catalyst, refines the attack's coherence. Demonstrated on a linear three-qubit system, our approach shows that such attacks can significantly disrupt diverse quantum protocols, sometimes reducing accuracy to random guessing, while remaining effective and stealthy even under realistic hardware parameter variations. We further propose a protocol-level detection strategy based on observable attack signatures, showing that stealthy attacks can be exposed through targeted monitoring and providing a foundation for future defense-in-depth in quantum cloud platforms.

quant-ph↗

arXiv2025

AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-based Heterogeneous Systems

The rapid adoption of chiplet-based heterogeneous integration is reshaping semiconductor design by enabling modular, scalable, and faster time-to-market solutions for AI and high-performance computing. However, multi-vendor assembly in post-fabrication environments fragments the supply chain and exposes SiP systems to serious security threats, including cloning, overproduction, and chiplet substitution. Existing authentication solutions depend on trusted integrators or centralized security anchors, which can expose sensitive data or create single points of failure. We introduce AuthenTree, a distributed authentication framework that leverages multi-party computation (MPC) in a scalable tree-based architecture, removing the need for dedicated security hardware or centralized trust. AuthenTree enables secure chiplet validation without revealing raw signatures, distributing trust across multiple integrator chiplets. Our evaluation in five SiP benchmarks demonstrates that AuthenTree imposes minimal overhead, with an area as low as 0.48% (7,000 sq-micrometers), an overhead power under 0.5%, and an authentication latency below 1 microsecond, surpassing previous work in some cases by 700 times. These results establish AuthenTree as an efficient, robust, and scalable solution for next-generation chiplet-based security in zero-trust SiP environments.

cs.CR↗

arXiv2025

ECOLogic: Enabling Circular, Obfuscated, and Adaptive Logic via eFPGA-Augmented SoCs

Traditional hardware platforms - ASICs and FPGAs - offer competing trade-offs among performance, flexibility, and sustainability. ASICs provide high efficiency but are inflexible post-fabrication, require costly re-spins for updates, and expose IPs to piracy risks. FPGAs offer reconfigurability and reuse, yet suffer from substantial area, power, and performance overheads, resulting in higher carbon footprints. We present ECOLogic, a hybrid design paradigm that embeds lightweight eFPGA fabric within ASICs to enable secure, updatable, and resource-aware computation. Central to this architecture is ECOScore, a quantitative scoring framework that evaluates IPs based on adaptability, piracy threat, performance tolerance, and resource fit to guide RTL partitioning. Evaluated across six diverse SoC modules, ECOLogic retains an average of 90 percent ASIC-level performance (up to 2 GHz), achieves 9.8 ns timing slack (versus 5.1 ns in FPGA), and reduces power by 480 times on average. Moreover, sustainability analysis shows a 99.7 percent reduction in deployment carbon footprint and 300 to 500 times lower emissions relative to FPGA-only implementations. These results position ECOLogic as a high-performance, secure, and environmentally sustainable solution for next-generation reconfigurable systems.

cs.AR↗

arXiv2025

Pulse-Level Simulation of Crosstalk Attacks on Superconducting Quantum Hardware

Hardware crosstalk in multi-tenant superconducting quantum computers poses a severe security threat, allowing adversaries to induce targeted errors across tenant boundaries by injecting carefully engineered pulses. We present a simulation-based study of active crosstalk attacks at the pulse level, analyzing how adversarial control of pulse timing, shape, amplitude, and coupling can disrupt a victim's computation. Our framework models the time-dependent dynamics of a three-qubit system in the rotating frame, capturing both always-on couplings and injected drive pulses. We examine two attack strategies: attacker-first (pulse before victim operation) and victim-first (pulse after), and systematically identify the pulse and coupling configurations that cause the largest logical errors. Protocol-level experiments on quantum coin flip and XOR classification circuits show that some protocols are highly vulnerable to these attacks, while others remain robust. Based on these findings, we discuss practical methods for detection and mitigation to improve security in quantum cloud platforms.

quant-ph↗

arXiv2025

SoK: Securing the Final Frontier for Cybersecurity in Space-Based Infrastructure

With the advent of modern technology, critical infrastructure, communications, and national security depend increasingly on space-based assets. These assets, along with associated assets like data relay systems and ground stations, are, therefore, in serious danger of cyberattacks. Strong security defenses are essential to ensure data integrity, maintain secure operations, and protect assets in space and on the ground against various threats. Previous research has found discrete vulnerabilities in space systems and suggested specific solutions to address them. Such research has yielded valuable insights, but lacks a thorough examination of space cyberattack vectors and a rigorous assessment of the efficacy of mitigation techniques. This study tackles this issue by taking a comprehensive approach to analyze the range of possible space cyber-attack vectors, which include ground, space, satellite, and satellite constellations. In order to address the particular threats, the study also assesses the efficacy of mitigation measures that are linked with space infrastructures and proposes a Risk Scoring Framework. Based on the analysis, this paper identifies potential research challenges for developing and testing cutting-edge technology solutions, encouraging robust cybersecurity measures needed in space.

cs.CR↗

arXiv2025

VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs

The rapid adoption of large language models(LLMs) in hardware design has primarily focused on generating functionally correct Verilog code, overlooking critical Power Performance-Area(PPA) metrics essential for industrial-grade designs. To bridge this gap, we propose VeriOpt, a novel framework that leverages role-based prompting and PPA-aware optimization to enable LLMs to produce high-quality, synthesizable Verilog. VeriOpt structures LLM interactions into specialized roles (e.g., Planner, Programmer, Reviewer, Evaluator) to emulate human design workflows, while integrating PPA constraints directly into the prompting pipeline. By combining multi-modal feedback (e.g., synthesis reports, timing diagrams) with PPA aware prompting, VeriOpt achieves PPA-efficient code generation without sacrificing functional correctness. Experimental results demonstrate up to 88% reduction in power, 76% reduction in area and 73% improvement in timing closure compared to baseline LLM-generated RTL, validated using industry standard EDA tools. At the same time achieves 86% success rate in functionality evaluation. Our work advances the state-of-the-art AI-driven hardware design by addressing the critical gap between correctness and quality, paving the way for reliable LLM adoption in production workflows.

cs.SE↗

arXiv2025

SAFE-SiP: Secure Authentication Framework for System-in-Package Using Multi-party Computation

The emergence of chiplet-based heterogeneous integration is transforming the semiconductor, AI, and high-performance computing industries by enabling modular designs and improved scalability. However, assembling chiplets from multiple vendors after fabrication introduces a complex supply chain that raises serious security concerns, including counterfeiting, overproduction, and unauthorized access. Current solutions often depend on dedicated security chiplets or changes to the timing flow, which assume a trusted SiP integrator. This assumption can expose chiplet signatures to other vendors and create new attack surfaces. This work addresses those vulnerabilities using Multi-party Computation (MPC), which enables zero-trust authentication without disclosing sensitive information to any party. We present SAFE-SiP, a scalable authentication framework that garbles chiplet signatures and uses MPC for verifying integrity, effectively blocking unauthorized access and adversarial inference. SAFE-SiP removes the need for a dedicated security chiplet and ensures secure authentication, even in untrusted integration scenarios. We evaluated SAFE-SiP on five RISC-V-based System-in-Package (SiP) designs. Experimental results show that SAFE-SiP incurs minimal power overhead, an average area overhead of only 3.05%, and maintains a computational complexity of 2^192, offering a highly efficient and scalable security solution.

cs.CR↗

arXiv2025

Security Vulnerabilities in Quantum Cloud Systems: A Survey on Emerging Threats

Quantum computing is becoming increasingly widespread due to the potential and capabilities to solve complex problems beyond the scope of classical computers. As Quantum Cloud services are adopted by businesses and research groups, they allow for greater progress and application in many fields. However, the inherent vulnerabilities of these environments pose significant security concerns. This survey delivers a comprehensive analysis of the security challenges that emerged in quantum cloud systems, with a distinct focus on multi-tenant vulnerabilities and the classical-quantum interface. Key threats such as crosstalk attacks, quantum-specific side-channel vulnerabilities, and insider threats are all examined, as well as their effects on the confidentiality, integrity, and availability of quantum circuits. The design and implementation of various quantum architectures from quantum cloud providers are also discussed. In addition, this paper delves into emerging quantum security solutions and best practices to mitigate these risks. This survey offers insights into current research gaps and proposes future directions for secure and resilient quantum cloud infrastructures.

cs.CR↗

arXiv2025

Enhancing Quantum Dense Coding Robustness Using Information Entropy-Based Metrics

Superdense Coding is a cornerstone in secure quantum communication, exploiting pre-shared entanglement to encode two classical bits within a single qubit. However, noise and decoherence deteriorate entanglement quality, restricting both fidelity and channel capacity in practical settings. Traditional methods, such as error correcting codes or entanglement distillation, are generally inadequate for dynamically varying noise conditions. Moreover, reliance on fidelity alone may fail to capture more subtle noise effects. This work introduces an adaptive protocol that integrates the five-qubit perfect code with a novel global adaptive purification that avoids discarding entangled pairs. By monitoring two information entropy-based metrics, quantum discord (QD) and entanglement of formation (EoF) from pilot pairs, we dynamically tune a global unitary to counteract noise. Our simulations, under both amplitude and phase damping, indicate that this integrated strategy could significantly enhance superdense coding robustness while preserving high throughput, thereby offering a scalable pathway toward a high-capacity quantum internet.

quant-ph↗