arXiv subjects

Themistoklis Prodromakis

Publications and source records attributed to Themistoklis Prodromakis.

18 recordsLinked to original sources

arXiv2022

An Adiabatic Capacitive Artificial Neuron with RRAM-based Threshold Detection for Energy-Efficient Neuromorphic Computing

In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with `memimpedace' elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at 100 degree Celsius across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance's quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses).

cs.NE↗

arXiv2020

Hybrid CMOS/Memristor Circuit Design Methodology

RRAM technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate with examples an end-to-end design flow for RRAM-based electronics, from the introduction of a custom RRAM model into our chosen CAD tool to performing layout-versus-schematic and post-layout checks including the RRAM device. We envisage that this step-by-step guide to introducing RRAM into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with RRAM-enhanced systems.

cs.ET↗

arXiv2020

Analysing and Measuring the Performance ofMemristive Integrating Amplifiers

Recording reliably extracellular neural activities isan essential prerequisite for the development of bioelectronicsand neuroprosthetic applications. Recently, a fully differential,2-stage, integrating pre-amplifier was proposed for amplifyingand then digitising neural signals. The amplifier featured a finelytuneable offset that was used as a variable threshold detector.Given that the amplifier is integrating, the DC operating pointkeeps changing during integration, rendering traditional analysis(AC/DC) unsuitable. In this work, we analyse the operation ofthis circuit and propose alternative definitions for validating thenecessary key performance metrics, including: gain, bandwidth,offset tuning range and offset sensitivity with respect to thememory states of the employed memristors. The amplificationprocess is analysed largely through investigating the transientbehaviour during the integration phase. This benchmarkingapproach is finally leveraged for providing useful insights anddesign trade-offs of the memristor-based integrating amplifier.

cs.ET↗

arXiv2019

A system of different layers of abstraction for artificial intelligence

The field of artificial intelligence (AI) represents an enormous endeavour of humankind that is currently transforming our societies down to their very foundations. Its task, building truly intelligent systems, is underpinned by a vast array of subfields ranging from the development of new electronic components to mathematical formulations of highly abstract and complex reasoning. This breadth of subfields renders it often difficult to understand how they all fit together into a bigger picture and hides the multi-faceted, multi-layered conceptual structure that in a sense can be said to be what AI truly is. In this perspective we propose a system of five levels/layers of abstraction that underpin many AI implementations. We further posit that each layer is subject to a complexity-performance trade-off whilst different layers are interlocked with one another in a control-complexity trade-off. This overview provides a conceptual map that can help to identify how and where innovation should be targeted in order to achieve different levels of functionality, assure them for safety, optimise performance under various operating constraints and map the opportunity space for social and economic exploitation.

cs.CY↗

arXiv2018

Practical Implementation of Memristor-Based Threshold Logic Gates

Current advances in emerging memory technologies enable novel and unconventional computing architectures for high-performance and low-power electronic systems, capable of carrying out massively parallel operations at the edge. One emerging technology, ReRAM, also known to belong in the family of memristors (memory resistors), is gathering attention due to its attractive features for logic and in-memory computing; benefits which follow from its technological attributes, such as nanoscale dimensions, low power operation and multi-state programming. At the same time, design with CMOS is quickly reaching its physical and functional limitations, and further research towards novel logic families, such as Threshold Logic Gates (TLGs) is scoped. TLGs constitute a logic family known for its high-speed and low power consumption, yet rely on conventional transistor technology. Introducing memristors enables a more affordable reconfiguration capability of TLGs. Through this work, we are introducing a physical implementation of a memristor-based current-mode TLG (MCMTLG) circuit and validate its design and operation through multiple experimental setups. We demonstrate 2-input and 3-input MCMTLG configurations and showcase their reconfiguration capability. This is achieved by varying memristive weights arbitrarily for shaping the classification decision boundary, thus showing promise as an alternative hardware-friendly implementation of Artificial Neural Networks (ANNs). Through the employment of real memristor devices as the equivalent of synaptic weights in TLGs, we are realizing components that can be used towards an in-silico classifier.

cs.ET↗

arXiv2017

A geographically distributed bio-hybrid neural network with memristive plasticity

Throughout evolution the brain has mastered the art of processing real-world inputs through networks of interlinked spiking neurons. Synapses have emerged as key elements that, owing to their plasticity, are merging neuron-to-neuron signalling with memory storage and computation. Electronics has made important steps in emulating neurons through neuromorphic circuits and synapses with nanoscale memristors, yet novel applications that interlink them in heterogeneous bio-inspired and bio-hybrid architectures are just beginning to materialise. The use of memristive technologies in brain-inspired architectures for computing or for sensing spiking activity of biological neurons8 are only recent examples, however interlinking brain and electronic neurons through plasticity-driven synaptic elements has remained so far in the realm of the imagination. Here, we demonstrate a bio-hybrid neural network (bNN) where memristors work as "synaptors" between rat neural circuits and VLSI neurons. The two fundamental synaptors, from artificial-to-biological (ABsyn) and from biological-to- artificial (BAsyn), are interconnected over the Internet. The bNN extends across Europe, collapsing spatial boundaries existing in natural brain networks and laying the foundations of a new geographically distributed and evolving architecture: the Internet of Neuro-electronics (IoN).

cs.ET↗

arXiv2017

Spike sorting using non-volatile metal-oxide memristors

Electrophysiological techniques have improved substantially over the past years to the point that neuroprosthetics applications are becoming viable. This evolution has been fuelled by the advancement of implantable microelectrode technologies that have followed their own version of Moore's scaling law. Similarly to electronics, however, excessive data-rates and strained power budgets require the development of more efficient computation paradigms for handling neural data in-situ, in particular the computationally heavy task of events classification. Here, we demonstrate how the intrinsic analogue programmability of memristive devices can be exploited to perform spike-sorting. We then show how combining memristors with standard logic enables efficient in-silico template matching. Leveraging the physical properties of nanoscale memristors allows us to implement ultra-compact analogue circuits for neural signal processing at the power cost of digital.

cs.ET↗

arXiv2017

A compact Verilog-A ReRAM switching model

The translation of emerging application concepts that exploit Resistive Random Access Memory (ReRAM) into large-scale practical systems requires realistic, yet computationally efficient, empirical models that can capture all observed physical devices. Here, we present a Verilog-A ReRAM model built upon experimental routines performed on TiOx-based prototypes. This model was based on custom biasing protocols, specifically designed to reveal device switching rate dependencies on a) bias voltage and b) initial resistive state. Our model is based on the assumption that a stationary switching rate surface m(R,v) exists for sufficiently low voltage stimulation. The proposed model comes in compact form as it is expressed by a simple voltage dependent exponential function multiplied with a voltage and initial resistive state dependent second order polynomial expression, which makes it suitable for fast and/or large-scale simulations.

cs.ET↗

arXiv2016

Sub 100nW volatile nano-metal-oxide memristor as synaptic-like encoder of neuronal spikes

Advanced neural interfaces mediate a bio-electronic link between the nervous system and microelectronic devices, bearing great potential as innovative therapy for various diseases. Spikes from a large number of neurons are recorded leading to creation of big data that require on-line processing under most stringent conditions, such as minimal power dissipation and on-chip space occupancy. Here, we present a new concept where the inherent volatile properties of a nano-scale memristive device are used to detect and compress information on neural spikes as recorded by a multi-electrode array. Simultaneously, and similarly to a biological synapse, information on spike amplitude and frequency is transduced in metastable resistive state transitions of the device, which is inherently capable of self-resetting and of continuous encoding of spiking activity. Furthermore, operating the memristor in a very high resistive state range reduces its average in-operando power dissipation to less than 100 nW, demonstrating the potential to build highly scalable, yet energy-efficient on-node processors for advanced neural interfaces.

cs.ET↗

arXiv2016

Practical Demonstration of a Memristive Fuse

Since its inception the memristive fuse has been a good example of how small numbers of memristors can be combined to obtain useful behaviours unachievable by individual devices. In this work, we link the memristive fuse concept with that of the Complementary Resistive Switch (CRS), exploit that link to experimentally demonstrate a practical memristive fuse using TiOx-based ReRAM cells and explain its basic operational principles. The fuse is stimulated by trains of identical pulses where successive pulse trains feature opposite polarities. In response, we observe a gradual (analogue) drop in resistive state followed by a gradual recovery phase regardless of input stimulus polarity; echoing traditional, binary CRS behaviour. This analogue switching property opens the possibility of operating the memristive fuse as a single-component step change detector. Moreover, we discover that the characteristics of the individual memristors used to demonstrate the memristive fuse concept in this work allow our fuse to be operated in a regime where one of the two constituent devices can be switched largely independently from the other. This property, not present in the traditional CRS, indicates that the inherently analogue memristive fuse architecture may support additional operational flexibility through e.g. allowing finer control over its resistive state.

cs.ET↗

arXiv2016

Emulating long-term synaptic dynamics with memristive devices

The potential of memristive devices is often seeing in implementing neuromorphic architectures for achieving brain-like computation. However, the designing procedures do not allow for extended manipulation of the material, unlike CMOS technology, the properties of the memristive material should be harnessed in the context of such computation, under the view that biological synapses are memristors. Here we demonstrate that single solid-state TiO2 memristors can exhibit associative plasticity phenomena observed in biological cortical synapses, and are captured by a phenomenological plasticity model called triplet rule. This rule comprises of a spike-timing dependent plasticity regime and a classical hebbian associative regime, and is compatible with a large amount of electrophysiology data. Via a set of experiments with our artificial, memristive, synapses we show that, contrary to conventional uses of solid-state memory, the co-existence of field- and thermally-driven switching mechanisms that could render bipolar and/or unipolar programming modes is a salient feature for capturing long-term potentiation and depression synaptic dynamics. We further demonstrate that the non-linear accumulating nature of memristors promotes long-term potentiating or depressing memory transitions.

cs.ET↗

arXiv2015

Memristive integrative sensors for neuronal activity

The advent of advanced neuronal interfaces offers great promise for linking brain functions to electronics. A major bottleneck in achieving this is real-time processing of big data that imposes excessive requirements on bandwidth, energy and computation capacity; limiting the overall number of bio-electronic links. Here, we present a novel monitoring system concept that exploits the intrinsic properties of memristors for processing neural information in real time. We demonstrate that the inherent voltage thresholds of solid-state TiOx memristors can be useful for discriminating significant neural activity, i.e. spiking events, from noise. When compared with a multi-dimensional, principal component feature space threshold detector, our system is capable of recording the majority of significant events, without resorting to computationally heavy off-line processing. We also show a memristive integrating sensing array that discriminates neuronal activity recorded in-vitro. We prove that information on spiking event amplitude is simultaneously transduced and stored as non-volatile resistive state transitions, allowing for more efficient data compression, demonstrating the memristors' potential for building scalable, yet energy efficient on-node processors for big data.

cs.ET↗

arXiv2015

Spatially resolved TiOx phases in RRAM conductive nanofilaments using soft X-ray spectromicroscopy

Reduction in metal-oxide thin films has been suggested as the key mechanism responsible for forming conductive nanofilaments within solid-state memory devices, enabling their resistive switching capacity. The quantitative spatial identification of such filaments is a daunting task, particularly for metal-oxides capable of exhibiting multiple phases as in the case of TiOx. Here, we spatially resolve and chemically characterize distinct TiOx phases in localized regions of a TiOx-based memristive device by combining full-field transmission X-ray microscopy with soft X-ray spectroscopic analysis that is performed on lamella samples. We particularly show that electrically pre-switched devices in low-resistive states comprise reduced disordered phases with O/Ti ratios close to Ti2O3 stoichiometry that aggregate in a ~ 100 nm filamentary region electrically conducting the top and bottom electrodes of the devices. We have also identified crystalline rutile and orthorhombic-like TiO2 phases in the region adjacent to the filament, suggesting that the temperature increases locally up to 1000 K, validating the role of Joule heating in resistive switching. Contrary to previous studies, our approach enables to simultaneously investigate morphological and chemical changes in a quantitative manner without incurring difficulties imposed by interpretation of electron diffraction patterns acquired via conventional electron microscopy techniques.

cond-mat.mtrl-sci↗

arXiv2015

Emulating short-term synaptic dynamics with memristive devices

Neuromorphic architectures offer great promise for achieving computation capacities beyond conventional Von Neumann machines. The essential elements for achieving this vision are highly scalable synaptic mimics that do not undermine biological fidelity. Here we demonstrate that single solid-state TiO2 memristors can exhibit non-associative plasticity phenomena observed in biological synapses, supported by their metastable memory state transition properties. We show that, contrary to conventional uses of solid-state memory, the existence of rate-limiting volatility is a key feature for capturing short-term synaptic dynamics. We also show how the temporal dynamics of our prototypes can be exploited to implement spatio-temporal computation, demonstrating the memristors full potential for building biophysically realistic neural processing systems.

cs.ET↗

arXiv2013

Computing shortest paths in 2D and 3D memristive networks

Global optimisation problems in networks often require shortest path length computations to determine the most efficient route. The simplest and most common problem with a shortest path solution is perhaps that of a traditional labyrinth or maze with a single entrance and exit. Many techniques and algorithms have been derived to solve mazes, which often tend to be computationally demanding, especially as the size of maze and number of paths increase. In addition, they are not suitable for performing multiple shortest path computations in mazes with multiple entrance and exit points. Mazes have been proposed to be solved using memristive networks and in this paper we extend the idea to show how networks of memristive elements can be utilised to solve multiple shortest paths in a single network. We also show simulations using memristive circuit elements that demonstrate shortest path computations in both 2D and 3D networks, which could have potential applications in various fields.

physics.comp-ph↗

arXiv2013

Integration of nanoscale memristor synapses in neuromorphic computing architectures

Conventional neuro-computing architectures and artificial neural networks have often been developed with no or loose connections to neuroscience. As a consequence, they have largely ignored key features of biological neural processing systems, such as their extremely low-power consumption features or their ability to carry out robust and efficient computation using massively parallel arrays of limited precision, highly variable, and unreliable components. Recent developments in nano-technologies are making available extremely compact and low-power, but also variable and unreliable solid-state devices that can potentially extend the offerings of availing CMOS technologies. In particular, memristors are regarded as a promising solution for modeling key features of biological synapses due to their nanoscale dimensions, their capacity to store multiple bits of information per element and the low energy required to write distinct states. In this paper, we first review the neuro- and neuromorphic-computing approaches that can best exploit the properties of memristor and-scale devices, and then propose a novel hybrid memristor-CMOS neuromorphic circuit which represents a radical departure from conventional neuro-computing approaches, as it uses memristors to directly emulate the biophysics and temporal dynamics of real synapses. We point out the differences between the use of memristors in conventional neuro-computing architectures and the hybrid memristor-CMOS circuit proposed, and argue how this circuit represents an ideal building block for implementing brain-inspired probabilistic computing paradigms that are robust to variability and fault-tolerant by design.

cs.ET↗

arXiv2012

Modelling of Current Percolation Channels in Emerging Resistive Switching Elements

Metallic oxides encased within Metal-Insulator-Metal (MIM) structures can demonstrate both unipolar and bipolar switching mechanisms, rendering them the capability to exhibit a multitude of resistive states and ultimately function as memory elements. Identifying the vital physical mechanisms behind resistive switching can enable these devices to be utilized more efficiently, reliably and in the long-term. In this paper, we present a new approach for analysing resistive switching by modelling the active core of two terminal devices as 2D and 3D grid circuit breaker networks. This model is employed to demonstrate that substantial resistive switching can only be supported by the formation of continuous current percolation channels, while multi-state capacity is ascribed to the establishment and annihilation of multiple channels.

cond-mat.mes-hall↗

arXiv2011

A Biomimetic Model of the Outer Plexiform Layer by Incorporating Memristive Devices

In this paper we present a biorealistic model for the first part of the early vision processing by incorporating memristive nanodevices. The architecture of the proposed network is based on the organisation and functioning of the outer plexiform layer (OPL) in the vertebrate retina. We demonstrate that memristive devices are indeed a valuable building block for neuromorphic architectures, as their highly non-linear and adaptive response could be exploited for establishing ultra-dense networks with similar dynamics to their biological counterparts. We particularly show that hexagonal memristive grids can be employed for faithfully emulating the smoothing-effect occurring at the OPL for enhancing the dynamic range of the system. In addition, we employ a memristor-based thresholding scheme for detecting the edges of grayscale images, while the proposed system is also evaluated for its adaptation and fault tolerance capacity against different light or noise conditions as well as distinct device yields.

cs.CV↗