arXiv subjects

Timothy G. Constandinou

Publications and source records attributed to Timothy G. Constandinou.

9 recordsLinked to original sources

arXiv2026

A mixed-signal analogue front-end for brain-implantable neural interfaces using a digital fixed-point IIR filter and bulk offset cancellation

Advances in miniaturised implantable neural electronics have paved the way for therapeutic brain-computer interfaces with clinical potential for movement disorders, epilepsy, and broader neurological applications. This paper presents a mixed-signal analogue front end (AFE) designed to record simultaneously both extracellular action potentials (EAPs) and local field potentials (LFPs). The feedforward path integrates a low-noise amplifier (LNA) and a successive-approximation-register (SAR) analogue-to-digital converter (ADC), while the feedback path employs a fixed-point infinite-impulse-response (IIR) Chebyshev Type II low-pass filter to suppress sub-mHz components via bulk-voltage control of the LNA input differential pair using two R-2R pseudo-resistor digital-to-analogue converters (DACs). The proposed AFE employs a low-power (LP) mode and an offset-cancellation high-performance (HP) mode. The proposed AFE achieves 40.55 dB gain and supports neural recording from 0.1 Hz to 5.705 / 9.66 kHz (LP / HP), with typical input-referred noise of 3.9 / 6.615 uVrms in the LFP band and 11.42 / 11.11 uVrms in the EAP band (LP / HP). Its typical power per channel is 5.44 uW (LP) and 11.35 uW (HP), while it occupies 0.198 mm2.

eess.SP↗

arXiv2026

Towards Radar-Agnostic Gait Analysis Across UWB and FMCW Systems

Radar sensing has emerged in recent years as a promising solution for unobtrusive and continuous in-home gait monitoring. This study evaluates whether a unified processing framework can be applied to radar-based spatiotemporal gait analysis independent of radar modality. The framework is validated using collocated impulse-radio ultra-wideband (IR-UWB) and frequency-modulated continuous-wave (FMCW) radars under identical processing settings, without modality-specific tuning, during repeated overground walking trials with 10 healthy participants. A modality-independent approach for automatic walking-segment identification is also introduced to ensure fair and reproducible modality performance assessment. Clinically relevant spatiotemporal gait parameters, including stride time, stride length, walking speed, swing time, and stance time, extracted from each modality were compared against gold-standard motion capture reference estimates. Across all parameters, both radar modalities achieved comparably high mean estimation accuracy in the range of 85-98%, with inter-modality differences remaining below 4.1%, resulting in highly overlapping accuracy distributions. Correlation and Bland-Altman analyses revealed minimal bias, comparable limits of agreement, and strong agreement with reference estimates, while intraclass correlation analysis demonstrated high consistency between radar modalities. These findings indicate that no practically meaningful performance differences arise from radar modality when using a shared processing framework, supporting the feasibility of radar-agnostic gait analysis systems.

eess.SP↗

arXiv2022

An Open-Source RRAM Compiler

Memory compilers are necessary tools to boost the design procedure of digital circuits. However, only a few are available to academia. Resistive Random Access Memory (RRAM) is characterised by high density, high speed, non volatility and is a potential candidate of future digital memories. To the best of the authors' knowledge, this paper presents the first open source RRAM compiler for automatic memory generation including its peripheral circuits, verification and timing characterisation. The RRAM compiler is written with Cadence SKILL programming language and is integrated in Cadence environment. The layout verification procedure takes place in Siemens Mentor Calibre tool. The technology used by the compiler is TSMC 180nm. This paper analyses the novel results of a plethora of M x N RRAMs generated by the compiler, up to M = 128, N = 64 and word size B = 16 bits, for clock frequency equal to 12.5 MHz. Finally, the compiler achieves density of up to 0.024 Mb/mm2.

cs.ET↗

arXiv2022

A CMOS-based Characterisation Platform for Emerging RRAM Technologies

Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device's resistance range to be between 1k$Ω$ and 10M$Ω$ with a minimum voltage range of $\pm$1.5V on the device.

cs.ET↗

arXiv2021

Hybrid CMOS/Memristor Circuit Design Methodology

RRAM technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate with examples an end-to-end design flow for RRAM-based electronics, from the introduction of a custom RRAM model into our chosen CAD tool to performing layout-versus-schematic and post-layout checks including the RRAM device. We envisage that this step-by-step guide to introducing RRAM into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with RRAM-enhanced systems.

cs.ET↗

arXiv2021

Hermetic chip-scale packaging using Au:Sn eutectic bonding for implantable devices

Advancements in miniaturisation and new capabilities of implantable devices impose a need for the development of compact, hermetic, and CMOS-compatible micro packaging methods. Gold-tin-based eutectic bonding presents the potential for achieving low-footprint seals with low permeability to moisture at process temperatures below 350\degree C. In this paper, a method for the deposition of gold-tin eutectic alloy frames via sequential electroplating from commercially available solutions, with no special fabrication process, is described in detail. Bond quality was characterised through shear force measurements, scanning electron microscopy, visual inspection, and immersion tests. Characterisation of seals geometry, solder thickness, and bonding process parameters were evaluated, along with toxicity assessment of bonding layers to the human fibroblast cells. With a successful bond yield of over 70\% and no cytotoxic effect, AuSn eutectic bonding appears as a suitable method for the protection of integrated circuitry in implantable applications.

cond-mat.mtrl-sci↗

arXiv2021

Open-Source Memory Compiler for Automatic RRAM Generation and Verification

The lack of open-source memory compilers in academia typically causes significant delays in research and design implementations. This paper presents an open-source memory compiler that is directly integrated within the Cadence Virtuoso environment using physical verification tools provided by Mentor Graphics (Calibre). It facilitates the entire memory generation process from netlist generation to layout implementation, and physical implementation verification. To the best of our knowledge, this is the first open-source memory compiler that has been developed specifically to automate Resistive Random Access Memory (RRAM) generation. RRAM holds the promise of achieving high speed, high density and non-volatility. A novel RRAM architecture, additionally is proposed, and a number of generated RRAM arrays are evaluated to identify their worst case control line parasitics and worst case settling time across the memristors of their cells. The total capacitance of lines SEL, N and P is 5.83 fF/cell, 3.31 fF/cell and 2.48 fF/cell respectively, while the total calculated resistance for SEL is 1.28 Ohm/cell and 0.14 Ohm/cell for both N and P lines.

cs.ET↗

arXiv2019

A 68 uW 31 kS/s Fully-Capacitive Noise-Shaping SAR ADC with 102 dB SNDR

This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noise-shaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB. We propose a novel fully-capacitive topology which allows for high-speed asynchronous conversion together with a background calibration scheme to reduce the oversampling requirement by 10x compared to prior-art. A 0.18 um CMOS technology is used to demonstrate preliminary simulation results together with analytic measures that optimise parameter and topology selection. The proposed system is able to achieve a FoMS of 183 dB for a maximum signal bandwidth of 15.6 kHz while dissipating 68 uW from a 1.8 V supply. A peak SNDR of 102 dB is demonstrated for this rate with a 0.201 mm^2 area requirement.

cs.AR↗

arXiv2019

Decoding Hand Kinematics from Local Field Potentials Using Long Short-Term Memory (LSTM) Network

Local field potential (LFP) has gained increasing interest as an alternative input signal for brain-machine interfaces (BMIs) due to its informative features, long-term stability, and low frequency content. However, despite these interesting properties, LFP-based BMIs have been reported to yield low decoding performances compared to spike-based BMIs. In this paper, we propose a new decoder based on long short-term memory (LSTM) network which aims to improve the decoding performance of LFP-based BMIs. We compare offline decoding performance of the proposed LSTM decoder to a commonly used Kalman filter (KF) decoder on hand kinematics prediction tasks from multichannel LFPs. We also benchmark the performance of LFP-driven LSTM decoder against KF decoder driven by two types of spike signals: single-unit activity (SUA) and multi-unit activity (MUA). Our results show that LFP-driven LSTM decoder achieves significantly better decoding performance than LFP-, SUA-, and MUA-driven KF decoders. This suggests that LFPs coupled with LSTM decoder could provide high decoding performance, robust, and low power BMIs.

q-bio.NC↗