arXiv subjects

Tuomo Tanttu

Publications and source records attributed to Tuomo Tanttu.

At least 19 recordsLinked to original sources

arXiv2026

Dispersive Readout of a SiMOS Quantum Dot Using a Flip-Chip Integrated Microwave Resonator

Heterogeneous integration provides a promising route to combine semiconductor quantum dot devices and superconducting microwave circuits, while allowing each component to be fabricated using an optimized process flow. Here, we demonstrate a flip-chip integrated platform for dispersive readout of silicon metal-oxide semiconductor (SiMOS) quantum dot devices. A SiMOS double quantum dot chip is bonded to a superconducting aluminum resonator chip using indium bump interconnects to enable microwave coupling to the quantum dot gate. We show that the developed flip-chip process is compatible with cryogenic operation of both the SiMOS device and the superconducting resonator, and demonstrate resonator-based detection of charge transitions in the quantum dot system. The readout signal-to-noise ratio follows a dependence of $\sqrt{t}$ with the integration time, reaching SNR = 1 at an integration time of approximately 0.3 ms. These results establish flip-chip bonding as a viable integration approach for SiMOS quantum dot devices operating at both dc and microwave frequencies, with potential applications for resonator-based techniques such as spin-photon coupling.

cond-mat.mes-hall↗

arXiv2026

SiMOS quantum-dot spin qubits enabled by extreme-ultraviolet lithography

The realization of large-scale silicon quantum processors requires spin qubits compatible with advanced semiconductor manufacturing technologies, demanding lithographic processes that combine nanometer-scale precision with exceptional uniformity. Although the highest-performing silicon spin qubits demonstrated to date have relied on electron-beam (e-beam) lithography, its serial exposure process limits reproducibility studies and wafer-scale fabrication. Here, we demonstrate high-performance silicon metal-oxide-semiconductor (SiMOS) spin qubits fabricated using extreme-ultraviolet (EUV) lithography in a 300 mm semiconductor pilot line. We report wafer-scale quantum-dot uniformity metrics, including 100 % room-temperature gate-to-gate leakage yield and sub-nanometer control of critical gate dimensions. We characterize four double-dot systems realized in two triple-quantum-dot devices. Gate set tomography (GST) reveals consistently high fidelities across all four systems, with values up to 99.8 % for SPAM, 99.9 % for single-qubit gates, and 99.1 % for two-qubit gates. The devices exhibit highly reproducible exchange turn-on characteristics of 10-13 dec/V, indicating high fabrication uniformity enabled by EUV patterning. These results establish EUV lithography as a viable manufacturing technology for quantum processors based on high-fidelity SiMOS spin qubits.

cond-mat.mes-hall↗

arXiv2026

Optimal operating temperature for industry-compatible silicon spin quantum computing: colder is not necessarily better

Silicon spin qubits are a leading candidate for large-scale quantum computing owing to their compatibility with semiconductor manufacturing. However, scaling to useful fault-tolerant processors will likely generate thermal loads that exceed the cooling power available at millikelvin temperatures. Raising the operating temperature eases cooling requirements but reduces gate fidelity, increasing the overhead of quantum error correction. Identifying the operating temperature that minimizes total power consumption is therefore a key challenge for commercially viable quantum computers. Here, we use gate set tomography to benchmark two-qubit silicon chips fabricated in both industrial and academic environments over a range of temperatures. Elevated temperatures substantially shorten coherence times and increase gate and state-preparation-and-measurement infidelities. Based on these measurements, we develop a general power model for silicon quantum computers that combines cryogenic cooling requirements with error-correction overheads. We show that a finite optimal operating temperature exists and is strongly influenced by a crossover temperature near 1 K in current devices, above which gate fidelity degrades rapidly. These results connect device-level fidelity limitations to system-level power requirements, providing design guidelines for large-scale silicon quantum computers.

quant-ph↗

arXiv2026

Multi-Qubit Entanglement of Unit Cell Pairs in SiMOS

Spin qubits in silicon-MOS (SiMOS) quantum dots have recently demonstrated compatibility with existing industry standard CMOS fabrication techniques. These devices have routinely achieved single- and two-qubit gate fidelities above 99% and demonstrated highly entangled two-qubit Bell states in isolated double quantum dot (DQD) unit cells, however coupling between unit cells has remained challenging. In this work, we present a two unit cell, four-qubit SiMOS processor with universal controllability and fully parallelised state initialisation and readout. We use this processor to generate maximally entangled three-qubit states, including the Greenberger-Horne-Zeilinger (GHZ) state, and certify multipartite entanglement through violation of the classical Mermin-witness bound. By using a fully symmetric dynamically decoupled gate sequence to create our entangled states, we are able to preserve the lifetime of the entanglement beyond $T_2^*$, to a time limited instead by $T_2^\textrm{Hahn}$. These demonstrations pave a road to the scalable operation of larger SiMOS processors, and achieving high purity, long-lived multi-qubit entangled states in them.

quant-ph↗

arXiv2026

Gate Stack Engineering for High-Mobility and Low-Noise SiMOS Quantum Devices

We systematically investigate the interplay between materials engineering, quantum transport, and low-frequency charge noise in silicon metal--oxide--semiconductor (SiMOS) quantum devices. By combining Hall-bar transport measurements with charge-noise spectroscopy of gate-defined quantum dots, we identify correlations between gate-stack design, carrier mobility, and electrostatic noise, providing an experimental case study of material and process dependencies relevant to low-noise, high-mobility operation. Hall-bar studies reveal that increasing the atomic-layer-deposition temperature of Al$_2$O$_3$ markedly enhances mobility, whereas the choice of oxidant has little impact. Devices incorporating HfO$_2$ exhibit improved carrier mobility, an interesting observation that can plausibly be attributed to defect passivation associated with aluminum diffusion from the gate metal into the HfO$_2$ layer. Charge-noise measurements show a strong correlation between higher mobility and reduced noise, with TiPd-gated devices displaying both degraded transport and elevated charge noise. In contrast, the poly-Si-gated CMOS-foundry device achieves the lowest noise levels. Finally, dual-feedback dot--sensor stability mapping demonstrates enhanced charge stability in devices with the gate stacks studied here, underscoring their promise for scalable, high-fidelity silicon spin-qubit platforms.

cond-mat.mes-hall↗

arXiv2025

Mid-circuit logic executed in the qubit layer of a quantum processor

Practical quantum computers need to continuously exchange data between classical and quantum subsystems during a computation. Mid-circuit measurements of a qubits state are transferred to the classical electronics layer, and their outcome can inform feedforward operations that close the loop back to the quantum layer. These operations are crucial for fault-tolerant quantum computers, but the quantum-classical loop must be completed before the qubits decohere, presenting a substantial engineering challenge for full-scale systems comprising millions of qubits. Here we perform the first mid-circuit measurements in a system of silicon spin qubits, and show that feedforward operations can be performed without needing to route information to the classical layer. This in-layer approach leverages a backaction-driven control technique that has previously been considered a source of error. We benchmark our in-layer strategy, together with the standard FPGA-enabled approach, and analyse the performance of both methods using gate set tomography. Our results provide the first step towards moving resource-intensive classical processing into the quantum layer, an advance that could solve key engineering challenges, and drastically reduce the power budget of future quantum computers.

quant-ph↗

arXiv2025

Eight-Qubit Operation of a 300 mm SiMOS Foundry-Fabricated Device

Silicon spin qubits are a promising platform for quantum computing due to their high coherence, controllability, and CMOS manufacturability, yet scalable implementations have so far been limited to a few qubits. Here, to take a step towards larger qubit systems, we tune and coherently control an eight-dot linear array of silicon spin qubits fabricated in a 300~mm CMOS-compatible foundry process, establishing operational scalability beyond the two-qubit regime. All eight qubits are successfully tuned and characterized as four double-dot pairs, exhibiting Ramsey dephasing times $T_2^*$ up to 41(2)$~\mu$s and Hahn-echo coherence times $T_2^{\mathrm{Hahn}}$ up to 1.31(4)$~$ms. Readout of the central four qubits is achieved via a cascaded charge-sensing protocol, enabling high-fidelity measurements of the entire multi-qubit array in a two step process. Additionally, we demonstrate a two-qubit gate operation between adjacent qubits with low phase noise. We show that silicon spin qubit arrays can be scaled to medium-sized arrays of 8 qubits while maintaining system coherence.

quant-ph↗

arXiv2025

Coupling a $^{73}$Ge nuclear spin to an electrostatically defined quantum dot

Single nuclear spins in silicon are a promising resource for quantum technologies due to their long coherence times and excellent control fidelities. Qubits and qudits have been encoded on donor nuclei, with successful demonstrations of Bell states and quantum memories on the spin-1/2 $^{31}$P and cat-qubits on the spin-7/2 $^{123}$Sb nuclei. Isoelectronic nuclear spins coupled to gate-defined quantum dots, such as the naturally occurring $^{29}$Si isotope, possess no additional charge and allow for the coupled electron to be shuttled without destroying the nuclear spin coherence. Here, we demonstrate the coupling and readout of a spin-9/2 $^{73}$Ge nuclear spin to a gate-defined quantum dot in SiMOS. The $^{73}$Ge nucleus was implanted by isotope-selective ion-implantation. We observe the hyperfine interaction (HFI) to the coupled quantum dot electron and are able to tune it from 180 kHz to 350 kHz, through the voltages applied to the lateral gate electrodes. This work lays the foundation for future spin control experiments on the spin-9/2 qudit as well as more advanced experiments such as entanglement distribution between distant nuclear spins or repeated weak measurements.

cond-mat.mes-hall↗

arXiv2025

Interplay of Zeeman Splitting and Tunnel Coupling in Coherent Spin Qubit Shuttling

Spin shuttling offers a promising approach for developing scalable silicon-based quantum processors by addressing the connectivity limitations of quantum dots. In this work, we demonstrate high-fidelity bucket-brigade spin shuttling in a silicon MOS device, utilizing Pauli-spin-blockade readout. We achieve an average shuttling fidelity of \SI{99.8}{\percent}. The residual shuttling error is highly sensitive to the ratio between interdot tunnel coupling and Zeeman splitting, with tuning of these parameters enabling up to a 20-fold variation in error rate. An appropriate four-level Hamiltonian model supports our findings. These results provide valuable insights for optimizing high-performance spin-shuttling systems in future quantum architectures.

cond-mat.mes-hall↗

arXiv2025

Scalable quantum current source on commercial CMOS process technology

Many quantum technologies require a precise electrical current standard that can only be achieved with expensive cryogenics, or through the secondary standards, such as resistance or voltage. Silicon-based charge pumps could provide such a standard in an inherently scalable way, through their compatibility with complementary metal-oxide-semiconductor (CMOS) fabrication methods. However, coherent quantized charge transfer has so far been demonstrated only in nanoscale devices that are custom-fabricated in academic cleanrooms or research technology foundries. Here, we show that a CMOS device manufactured with commercial 22-nm process node can be used to define a quantum current standard in the International System of Units (SI). We measure an accuracy of (1.2 +/- 0.1)E-3 A/A at 50 MHz with reference to SI voltage and resistance standards in a pumped helium system. We then propose a practical monolithic CMOS chip that incorporates one million parallel connected charge pumps along with on-chip control electronics. This chip could be operated as a table-top primary standard that can be easily integrated with CMOS electronics, generating quantum currents of up to microampere levels.

physics.app-ph↗

arXiv2025

Enhancement of Electric Drive in Silicon Quantum Dots with Electric Quadrupole Spin Resonance

Quantum computation with electron spin qubits requires coherent and efficient manipulation of these spins, typically accomplished through the application of alternating magnetic or electric fields for electron spin resonance (ESR). In particular, electrical driving allows us to apply localized fields on the electrons, which benefits scale-up architectures. However, we have found that Electric Dipole Spin Resonance (EDSR) is insufficient for modeling the Rabi behavior in recent experimental studies. Therefore, we propose that the electron spin is being driven by a new method of electric spin qubit control which generalizes the spin dynamics by taking into account a quadrupolar contribution of the quantum dot: electric quadrupole spin resonance (EQSR). In this work, we explore the electric quadrupole driving of a quantum dot in silicon, specifically examining the cases of 5 and 13 electron occupancies.

cond-mat.mes-hall↗

arXiv2024

A 2x2 quantum dot array in silicon with fully tuneable pairwise interdot coupling

Recent advances in semiconductor spin qubits have achieved linear arrays exceeding ten qubits. Moving to two-dimensional (2D) qubit arrays is a critical next step to advance towards fault-tolerant implementations, but it poses substantial fabrication challenges, particularly because enabling control of nearest-neighbor entanglement requires the incorporation of interstitial exchange gates between quantum dots in the qubit architecture. In this work, we present a 2D array of silicon metal-oxide-semiconductor (MOS) quantum dots with tunable interdot coupling between all adjacent dots. The device is characterized at 4.2 K, where we demonstrate the formation and isolation of double-dot and triple-dot configurations. We show control of all nearest-neighbor tunnel couplings spanning up to 30 decades per volt through the interstitial exchange gates and use advanced modeling tools to estimate the exchange interactions that could be realized among qubits in this architecture. These results represent a significant step towards the development of 2D MOS quantum processors compatible with foundry manufacturing techniques.

cond-mat.mes-hall↗

arXiv2024

A 300 mm foundry silicon spin qubit unit cell exceeding 99% fidelity in all operations

Fabrication of quantum processors in advanced 300 mm wafer-scale complementary metal-oxide-semiconductor (CMOS) foundries provides a unique scaling pathway towards commercially viable quantum computing with potentially millions of qubits on a single chip. Here, we show precise qubit operation of a silicon two-qubit device made in a 300 mm semiconductor processing line. The key metrics including single- and two-qubit control fidelities exceed 99% and state preparation and measurement fidelity exceeds 99.9%, as evidenced by gate set tomography (GST). We report coherence and lifetimes up to $T_\mathrm{2}^{\mathrm{*}} = 30.4$ $\mu$s, $T_\mathrm{2}^{\mathrm{Hahn}} = 803$ $\mu$s, and $T_1 = 6.3$ s. Crucially, the dominant operational errors originate from residual nuclear spin carrying isotopes, solvable with further isotopic purification, rather than charge noise arising from the dielectric environment. Our results answer the longstanding question whether the favourable properties including high-fidelity operation and long coherence times can be preserved when transitioning from a tailored academic to an industrial semiconductor fabrication technology.

cond-mat.mes-hall↗

arXiv2024

Violating Bell's inequality in gate-defined quantum dots

Superior computational power promised by quantum computers utilises the fundamental quantum mechanical principle of entanglement. However, achieving entanglement and verifying that the generated state does not follow the principle of local causality has proven difficult for spin qubits in gate-defined quantum dots, as it requires simultaneously high concurrence values and readout fidelities to break the classical bound imposed by Bell's inequality. Here we employ heralded initialization and calibration via gate set tomography (GST), to reduce all relevant errors and push the fidelities of the full 2-qubit gate set above 99 %, including state preparation and measurement (SPAM). We demonstrate a 97.17 % Bell state fidelity without correcting for readout errors and violate Bell's inequality with a Bell signal of S = 2.731 close to the theoretical maximum of $2\sqrt{2}$. Our measurements exceed the classical limit even at elevated temperatures of 1.1 K or entanglement lifetimes of 100 $\mu s$.

cond-mat.mes-hall↗

arXiv2024

Spin Qubits with Scalable milli-kelvin CMOS Control

A key virtue of spin qubits is their sub-micron footprint, enabling a single silicon chip to host the millions of qubits required to execute useful quantum algorithms with error correction. With each physical qubit needing multiple control lines however, a fundamental barrier to scale is the extreme density of connections that bridge quantum devices to their external control and readout hardware. A promising solution is to co-locate the control system proximal to the qubit platform at milli-kelvin temperatures, wired-up via miniaturized interconnects. Even so, heat and crosstalk from closely integrated control have potential to degrade qubit performance, particularly for two-qubit entangling gates based on exchange coupling that are sensitive to electrical noise. Here, we benchmark silicon MOS-style electron spin qubits controlled via heterogeneously-integrated cryo-CMOS circuits with a low enough power density to enable scale-up. Demonstrating that cryo-CMOS can efficiently enable universal logic operations for spin qubits, we go on to show that mill-kelvin control has little impact on the performance of single- and two-qubit gates. Given the complexity of our milli-kelvin CMOS platform, with some 100-thousand transistors, these results open the prospect of scalable control based on the tight packaging of spin qubits with a chiplet style control architecture.

quant-ph↗

arXiv2023

Entangling gates on degenerate spin qubits dressed by a global field

Coherently dressed spins have shown promising results as building blocks for future quantum computers owing to their resilience to environmental noise and their compatibility with global control fields. This mode of operation allows for more amenable qubit architecture requirements and simplifies signal routing on the chip. However, multi-qubit operations, such as qubit addressability and two-qubit gates, are yet to be demonstrated to establish global control in combination with dressed qubits as a viable path to universal quantum computing. Here we demonstrate simultaneous on-resonance driving of degenerate qubits using a global field while retaining addressability for qubits with equal Larmor frequencies. Furthermore, we implement SWAP oscillations during on-resonance driving, constituting the demonstration of driven two-qubit gates. Significantly, our findings highlight the fragility of entangling gates between superposition states and how dressing can increase the noise robustness. These results represent a crucial milestone towards global control operation with dressed qubits. It also opens a door to interesting spin physics on degenerate spins.

cond-mat.mes-hall↗

arXiv2023

Wavelet correlation noise analysis for qubit operation variable time series

In quantum computing, characterizing the full noise profile of qubits can aid in increasing coherence times and fidelities by developing error-mitigating techniques specific to the noise present. This characterization also supports efforts in advancing device fabrication to remove sources of noise. Qubit properties can be subject to non-trivial correlations in space and time, for example, spin qubits in MOS quantum dots are exposed to noise originating from the complex glassy behavior of two-level fluctuator ensembles. Engineering progress in spin qubit experiments generates large amounts of data, necessitating analysis techniques from fields experienced in managing large data sets. Fields such as astrophysics, finance, and climate science use wavelet-based methods to enhance their data analysis. Here, we propose and demonstrate wavelet-based analysis techniques to decompose signals into frequency and time components, enhancing our understanding of noise sources in qubit systems by identifying features at specific times. We apply the analysis to a state-of-the-art two-qubit experiment in a pair of SiMOS quantum dots with feedback applied to relevant operation variables. The observed correlations serve to identify common microscopic causes of noise, such as two-level fluctuators and hyperfine coupled nuclei, as well as to elucidate pathways for multi-qubit operation with more scalable feedback systems.

quant-ph↗

arXiv2023

Real-time feedback protocols for optimizing fault-tolerant two-qubit gate fidelities in a silicon spin system

Recently, several groups have demonstrated two-qubit gate fidelities in semiconductor spin qubit systems above 99%. Achieving this regime of fault-tolerant compatible high fidelities is nontrivial and requires exquisite stability and precise control over the different qubit parameters over an extended period of time. This can be done by efficiently calibrating qubit control parameters against different sources of micro- and macroscopic noise. Here, we present several single- and two-qubit parameter feedback protocols, optimised for and implemented in state-of-the-art fast FPGA hardware. Furthermore, we use wavelet-based analysis on the collected feedback data to gain insight into the different sources of noise in the system. Scalable feedback is an outstanding challenge and the presented implementation and analysis gives insight into the benefits and drawbacks of qubit parameter feedback, as feedback related overhead increases. This work demonstrates a pathway towards robust qubit parameter feedback and systematic noise analysis, crucial for mitigation strategies towards systematic high-fidelity qubit operation compatible with quantum error correction protocols.

quant-ph↗