arXiv subjects

Utkarsh Singh

Publications and source records attributed to Utkarsh Singh.

21 records · Page 2Linked to original sources

arXiv2020

A Research Review on Detection and Classification of Power Quality Disturbances caused by Integration of Renewable Energy Sources

With the increased interest in integrating renewable energy sources (RES) such as wind power and solar into the power systems owing to their zero greenhouse gas emissions and the involvement of power converters for integration in grid, the detection, classification and mitigation of power quality events has become indispensable. For employing an appropriate mitigation technique, it is a pre-requisite to correctly classify the various types of disturbances in power quality. This paper, therefore, presents a detailed research reviews on detection and classification of power quality disturbances caused by the integration of renewable energy sources and associated works present in literature till date. Attempts are also made to highlight the current and future issues involved in the detection, classification and mitigation of PQ disturbances. Best efforts have been made to make this paper serve as a full-fledged reference for the future work in this field. A list of 230 research publications on the subject is also appended for quick reference.

eess.SP↗

arXiv2019

Comparing domain wall synapse with other Non Volatile Memory devices for on-chip learning in Analog Hardware Neural Network

Resistive Random Access Memory (RRAM) and Phase Change Memory (PCM) devices have been popularly used as synapses in crossbar array based analog Neural Network (NN) circuit to achieve more energy and time efficient data classification compared to conventional computers. Here we demonstrate the advantages of recently proposed spin orbit torque driven Domain Wall (DW) device as synapse compared to the RRAM and PCM devices with respect to on-chip learning (training in hardware) in such NN. Synaptic characteristic of DW synapse, obtained by us from micromagnetic modeling, turns out to be much more linear and symmetric (between positive and negative update) than that of RRAM and PCM synapse. This makes design of peripheral analog circuits for on-chip learning much easier in DW synapse based NN compared to that for RRAM and PCM synapses. We next incorporate the DW synapse as a Verilog-A model in the crossbar array based NN circuit we design on SPICE circuit simulator. Successful on-chip learning is demonstrated through SPICE simulations on the popular Fisher's Iris dataset. Time and energy required for learning turn out to be orders of magnitude lower for DW synapse based NN circuit compared to that for RRAM and PCM synapse based NN circuits.

physics.app-ph↗

arXiv2019

On-chip learning in a conventional silicon MOSFET based Analog Hardware Neural Network

On-chip learning in a crossbar array based analog hardware Neural Network (NN) has been shown to have major advantages in terms of speed and energy compared to training NN on a traditional computer. However analog hardware NN proposals and implementations thus far have mostly involved Non Volatile Memory (NVM) devices like Resistive Random Access Memory (RRAM), Phase Change Memory (PCM), spintronic devices or floating gate transistors as synapses. Fabricating systems based on RRAM, PCM or spintronic devices need in-house laboratory facilities and cannot be done through merchant foundries, unlike conventional silicon based CMOS chips. Floating gate transistors need large voltage pulses for weight update, making on-chip learning in such systems energy inefficient. This paper proposes and implements through SPICE simulations on-chip learning in analog hardware NN using only conventional silicon based MOSFETs (without any floating gate) as synapses since they are easy to fabricate. We first model the synaptic characteristic of our single transistor synapse using SPICE circuit simulator and benchmark it against experimentally obtained current-voltage characteristics of a transistor. Next we design a Fully Connected Neural Network (FCNN) crossbar array using such transistor synapses. We also design analog peripheral circuits for neuron and synaptic weight update calculation, needed for on-chip learning, again using conventional transistors. Simulating the entire system on SPICE simulator, we obtain high training and test accuracy on the standard Fisher's Iris dataset, widely used in machine learning. We also compare the speed and energy performance of our transistor based implementation of analog hardware NN with some previous implementations of NN with NVM devices and show comparable performance with respect to on-chip learning.

cs.NE↗