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V. Cavallini

Publications and source records attributed to V. Cavallini.

3 recordsLinked to original sources
arXiv2026

A flexible DAQ system for the Timepix4 ASIC in the 4DPHOTON project

This paper presents the design and implementation of a flexible data acquisition system13 developed for the Timepix4 ASIC within the 4DPHOTON project. The system is based on a modular14 FPGA-centric architecture combining high-speed serial readout, Ethernet-based data transport,15 and deterministic multi-board synchronization. The hardware platform includes a scalable stack16 composed of commercial FPGA carrier boards, FMC-based interface electronics, detector-specific17 chipboards, and a dedicated Trigger Logic Unit for synchronized operation.18 The firmware architecture separates control and data paths, enabling independent configuration19 and high-throughput acquisition through UDP over 10 GbE links. The design supports zero-back-20 pressure operation toward the ASIC and allows adaptation of the readout bandwidth to different21 experimental conditions. Synchronization between multiple DAQ systems is achieved through22 a common clock and trigger distribution network, experimentally demonstrated with sub-100 ps23 precision.24 The system has been developed to support detector characterization, laboratory measurements,25 and beam-test campaigns for the 4DPHOTON detector concept. Hardware organization, firmware26 architecture, synchronization strategy, and performance measurements are presented.

physics.ins-det↗
arXiv2021

Development of a single-photon imaging detector with pixelated anode and integrated digital read-out

We present the development of a single-photon detector and the connected read-out electronics. This `hybrid' detector is based on a vacuum tube, transmission photocathode, microchannel plate and a pixelated CMOS read-out anode encapsulating the analog and digital-front end electronics. This assembly will be capable of detecting up to $10^9$ photons per second with simultaneous measurement of position and time. The pixelated read-out anode used is based on the Timepix4 ASIC ($65~\mathrm{nm}$ CMOS technology) designed in the framework of the Medipix4 collaboration. This ASIC is an array of $512\times448$ pixels distributed on a $55~\mathrm{μm}$ square pitch, with a sensitive area of $\sim 7~\mathrm{cm}^2$. It features $50$-$70~\mathrm{e^{-}}$ equivalent noise charge, a maximum rate of $2.5~\mathrm{Ghits/s}$, and allows to time-stamp the leading-edge time and to measure the Time-over-Threshold (ToT) for each pixel. The pixel-cluster position combined with its ToT information will allow to reach $5$-$10~\mathrm{μm}$ position resolution. This information can also be used to correct for the leading-edge time-walk achieving a timing resolution of the order of $10~\mathrm{ps}$. The detector will be highly compact thanks to the encapsulated front-end electronics allowing local data processing and digitization. An FPGA-based data acquisition board, placed far from the detector, will receive the detector hits using $16$ electro-optical links operated at $10.24~\mathrm{Gbps}$. The data acquisition board will decode the information and store the relevant data in a server for offline analysis. These performance will allow significant advances in particle physics, life sciences, quantum optics or other emerging fields where the detection of single photons with excellent timing and position resolutions are simultaneously required.

physics.ins-det↗