arXiv subjects

Vasili K. Semenov

Publications and source records attributed to Vasili K. Semenov.

12 recordsLinked to original sources

arXiv2025

Demonstration of Superconductor Shift Registers with Energy Dissipation Below Landauer's Thermodynamic Limit

We study energy dissipation and propagation of information encoded by Josephson vortices in two types of circular shift register: a) a uniform register composed of sections of discrete Josephson transmission lines (JTL) forming a closed loop with a flux pump allowing to change the number of moving fluxon; b) a nonuniform register composed of sections of the regular JTL and sections of JTLs utilizing nSQUIDs - dc-SQUIDs with negative inductance between their arms - instead of single Josephson junctions. nSQUIDs are parametric devices with a flexible double-well potential that were proposed as components for reversible computing. For the uniform register, we demonstrate the energy dissipation per bit-shift operation below the Landauer's thermodynamic limit $E_T=k_BTln2$ up to propagation delays of ~0.7 ns, corresponding to the circular information motion with frequencies up to ~1.4 GHz. This does not contradict Landauer's minimum energy requirement for computations since information is not destroyed. For the nonuniform register, we find the minimum energy dissipation per bit-shift of about 16$E_T$ and attribute this to a nonuniform movement of vortices and energy barriers between the regular JTL and nSQUID sections. Differences of Josephson vortex propagation in both types of circular registers are discussed based on the measured current-voltage characteristics, extracted effective resistance and the terminal speed of Josephson vortices, and their dependences on the number of moving vorticies. nSQUID inductance connecting JJs to the ground leads to an unusual type of lossless discrete transmission line with frequency-dependent impedance and propagation speed, both different from the regular JTLs.

cond-mat.supr-con↗

arXiv2025

Characterization of Flux Trapping in and Fabrication of Large-Scale Superconductor Circuits Using AC-Biased Shift Registers With 108500 Josephson Junctions

A variety of superconductor integrated circuits comprising six ac-powered SFQ shift registers with a total of 27078 bits and 108500 Josephson junctions (JJs) per 5 mm x 5 mm chip have been designed, fabricated, and tested to characterize flux trapping, fabrication process yield, and parameter spread. The six 4513-bit registers in the circuits have a common single-phase ac clock and individual input/output drivers enabling their parallel testing. We have investigated flux trapping in the circuits with various geometry, size, and distance between moats in two active ground planes (GPs), and containing up to three additional 'dummy' GPs, using multiple cooldowns through the critical temperature with various cooling rates and residual magnetic fields up to ~1.2 $μ$T. For the slit-type and square moats arrayed along the sides of the register cells, we have found a negligible effect of flux sequestered in the moats on the operating margins of the registers, and negligible probability of detrimental flux trapping outside of the moats. Circuits with 0.3-$μ$m-wide slit moats occupying <2% of the circuit area were fully operational in 100% of cooldowns, supporting the viability of VLSI superconductor digital circuits. We have found a strong enhancement of flux trapping outside of the moats in circuits with closely spaced GPs and determined a critical distance, t$_c$=0.6 $μ$m, between them. The presence of GPs spaced below t$_c$ rendered the circuits nonoperational in 100% of cooldowns. We have measured 30 chips with >3M JJs and determined individual cell margins in 138 registers to characterize the fabrication-related parameter spread and detect fabrication defects and flux-trapping events. By finding outlier cells in the statistical distribution of the individual cell margins, we detected about one defect per million JJs, in most cases causing magnetic flux trapping in the affected cell.

cond-mat.supr-con↗

arXiv2024

Development of a Neuromorphic Network Using BioSFQ Circuits

Superconductor electronics (SCE) appear promising for low energy applications. However, the achieved and projected circuit densities are insufficient for direct competition with CMOS technology. Original algorithms and nontraditional architectures are required for realizing SCE energy advantages for computing. Neuromorphic computing (NMC) is a commonly discussed deviation from conventional CMOS digital solutions. Instead of mimicking a conventional network of artificial neurons, we compose a network from the previously demonstrated single flux quantum (SFQ) electronics components which we termed bioSFQ. We present a design and operation of a new neuromorphic circuit containing a 3x3 array of bioSFQ cells - superconductor artificial neurons - capable of performing various analog functions and based on Josephson junction comparators with complementary outputs. The resultant asynchronous network closely resembles a three-layer perceptron. We also present superconductor analog memory and the memory Read/Write interface implemented with the neural network. The circuits were fabricated in the SFQ5ee process at MIT Lincoln Laboratory.

cond-mat.supr-con↗

arXiv2023

BioSFQ circuit family for neuromorphic computing: Bridging digital and analog domains of superconductor technologies

Superconductor single flux quantum (SFQ) technology is attractive for neuromorphic computing due to low energy dissipation and high, potentially up to 100 GHz, clock rates. We have recently suggested a new family of bioSFQ circuits (V.K. Semenov et al., IEEE TAS, vol. 32, no. 4, 1400105, 2022) where information is stored as a value of current in a superconducting loop and transferred as a rate of SFQ pulses propagating between the loops. This approach, in the simplest case dealing with positive numbers, requires single-line transfer channels. In the more general case of bipolar numbers, it requires dual-rail transfer channels. To address this need, we have developed a new comparator with a dual-rail output. This comparator is an essential part of a bipolar multiplier that has been designed, fabricated, and tested. We discuss bioSFQ circuits for implementing an analog bipolar divide operation $Y/X$ and a square root operation $X^{1/2}$. We discuss strategic advantages of the suggested bioSFQ approach, e.g., an inherently asynchronous character of bioSFQ cells which do not require explicit clock signals. As a result, bioSFQ circuits are free of racing errors and tolerant to occasional collision of propagating SFQ pulses. This tolerance is due to stochastic nature of data signals generated by comparators operating within their gray zone. The circuits were fabricated in the eight-niobium-layer fabrication process SFQ5ee developed for superconductor electronics at MIT Lincoln Laboratory.

cond-mat.supr-con↗

arXiv2021

A new family of bioSFQ logic/memory cells

Superconductor electronics (SCE) is competing to become a platform for efficient implementations of neuromorphic computing and deep learning algorithms (DLAs) with projects mostly concentrating on searching for gates that would better mimic behavior of real neurons. In contrast, we believe that most of the required components have already been demonstrated during the long history of SCE, whereas the missing part is how to organize these components to efficiently implement DLAs. We propose a family of logic/memory cells in which stored multi-bit data are encoded by quasi-analog currents or magnetic flux in superconductor loops while transmitted data are encoded as the rate of SFQ pulses. We designed, fabricated, and tested some of the basic cells to demonstrate a proof of concept, e.g., a unipolar and bipolar multipliers based on Josephson junction comparators. We coined the term bioSFQ to clearly connote close but distinguishable relations between the conventional SFQ electronics and its new neuromorphic paradigm.

cond-mat.supr-con↗

arXiv2021

SFQ bias for SFQ digital circuits

Superconductor electronics fabrication technology developed at MIT Lincoln Laboratory enables the development of VLSI digital circuits with millions of Josephson junctions per square centimeter. However, conventional DC and multi-phase AC biasing techniques already encounter serious challenges for scaling circuits above several hundred thousand junctions. In this work, we propose a novel AC-based biasing scheme for RSFQ-type logic families requiring DC bias. The major step toward this scheme is a superconducting AC/DC rectifier which we introduced at ASC 2014. Initially, we proposed to connect the rectifiers to 'payload cells' via superconducting inductors with large inductance in order to reduce parasitic effects of flux quantization. Recently, we discovered that this powering scheme works even better at a much lower value of the inductance, when it is just sufficient to hold only one or two flux quanta in the inductive loop between the converter and the payload. In this case, flux quantization in the loop becomes beneficial because the value of current fed into the payload is defined by the value of the coupling inductance. Therefore, our AC/SFQ converter powers the payload cell by a single flux quantum rather than by DC current. Such mode of operation is extremely energy efficient because the energy is used only to recover flux quantum consumed by the cell during the logic operation. We present designs of AC/SFQ converters comprising an AC/DC rectifier and a current conditioning circuit which we termed an SFQ filter. We also present test results and demonstrate AC/SFQ powering a payload circuit using circuits fabricated in a new, 150-nm node of Lincoln Laboratory fabrication technology using self-shunted Nb/AlOx-Al/Nb Josephson junctions with 600 $μ$A/$μ$$m^2$ critical current density and 200 nm minimum linewidth of inductors.

cond-mat.supr-con↗

arXiv2019

Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories

Arrays of Vortex Transitional (VT) memory cells with functional density up to $1 Mbit/cm^2$ have been designed, fabricated, and successfully demonstrated. This progress is due to recent advances in design optimization and in superconductor electronics fabrication achieved at MIT Lincoln Laboratory. As a starting point, we developed a demo array of VT cells for the 100-$μA/μm^2$ MIT LL fabrication process SFQ5ee with 8 niobium layers. The studied two-junction memory cell with a two-junction nondestructive readout occupied $168 μm^2$, resulting in an over $0.5 Mbit/cm^2$ functional density. Then, we reduced the cell area down to $99 μm^2$ (corresponding to over $0.9 Mbit/cm^2$ functional density) by utilizing self-shunted Josephson Junctions (JJs) with critical current density, $J_c$ of $600 μA/μm^2$ and eliminating shunt resistors. The fabricated high-$J_c$ memory cells were fully operational and possessed wide Read/Write current margins, quite close to the theoretically predicted values. We discuss approaches to further increasing the integration scale of superconductor memory and logic circuits: a) miniaturization of superconducting transformers by using soft magnetic materials; b) reduction of JJ area by using planar high-$J_c$ junctions similar to variable thickness bridges.

physics.app-ph↗

arXiv2017

Ring Oscillators for Clocking Reversible Superconducting Circuits and Fabrication Process Benchmarking

Existing concepts of reversible superconducting circuits as well as demonstrated adiabatic circuits require three-phase bias/clock signals generated by room temperature sources. A while ago, we suggested that a multi-phase bias/clock could be provided by a local Josephson junction-based generator. The generator looks like a long annular Josephson junction, only composed of discreet elements - junctions and inductors, and closed into a ring via a flux pump to inject any required number of vortices into the ring. A steady motion of the vortices forced by a uniformly distributed dc bias current applied to the ring is accompanied by a nearly harmonic ac currents flowing via the Josephson junctions (JJs) connected in series with small inductors. These ac currents serve as multi-phase bias/clock for nSQUID-based circuitry. To verify this concept and compare the dissipated energy with kBTln2 threshold, we developed a ring composed of 256 unshunted JJs with 20 μA target critical current, Ic. We investigated the behavior of the ring oscillator at each vortex count from 0 to 256. The measured critical current of the ring with vortices was about 0.1 μA per one JJ, which can be explained by unavoidable nonuniformity of the ring components and the influence of fluxes frozen near the ring. The corresponding energy dissipation, about 10kBT per passage of one vortex through one JJ, should be reduced further for prospective experiments with reversible circuits. However, obtained I-V characteristics could be of interest for scientists working with long Josephson junctions. Superiority of the fabrication process used in this work is demonstrated by the obtained about 200 times reduction of Ic of the ring with vortices with respect to a single comprising JJ, much larger than in any previously described case.

cond-mat.supr-con↗

arXiv2016

AC-Biased Shift Registers as Fabrication Process Benchmark Circuits and Flux Trapping Diagnostic Tool

We develop an ac-biased shift register introduced in our previous work (V.K. Semenov et al., IEEE Trans. Appl. Supercond., vol. 25, no. 3, 1301507, June 2015) into a benchmark circuit for evaluation of superconductor electronics fabrication technology. The developed testing technique allows for extracting margins of all individual cells in the shift register, which in turn makes it possible to estimate statistical distribution of Josephson junctions in the circuit. We applied this approach to successfully test registers having 8, 16, 36, and 202 thousand cells and, respectively, about 33000, 65000, 144000, and 809000 Josephson junctions. The circuits were fabricated at MIT Lincoln Laboratory, using a fully planarized process, 0.4 μm inductor linewidth, and 1.33x10^6 cm^-2 junction density. They are presently the largest operational superconducting SFQ circuits ever made. The developed technique distinguishes between hard defects (fabrication-related) and soft defects (measurement-related) and locates them in the circuit. The soft defects are specific to superconducting circuits and caused by magnetic flux trapping either inside the active cells or in the dedicated flux-trapping moats near the cells. The number and distribution of soft defects depend on the ambient magnetic field and vary with thermal cycling even if done in the same magnetic environment.

physics.ins-det↗

arXiv2014

Inductance of Circuit Structures for MIT LL Superconductor Electronics Fabrication Process with 8 Niobium Layers

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90-degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities > 10^6 Josephson junctions per cm^2 are discussed.

cond-mat.supr-con↗

arXiv2014

New AC-Powered SFQ Digital Circuits

Recent progress of Reciprocal Quantum Logic (RQL) has renewed interest in AC powering of superconductor digital circuits, which had been abandoned since the famous IBM project of 1970s. In this work we propose and demonstrate new AC-biased Single Flux Quantum (SFQ) circuits, and search for synergy of AC and currently dominating DC biasing schemes. As the first step, we suggest an on-chip AC/DC converter capable of feeding a few DC-biased gates surrounded by their AC-biased counterparts. As the second step, we introduce and present the first successful demonstration of a new AC-powered circuit - an 8192-bit shift register with over 32,800 Josephson junctions (JJs) and JJ density of about 6x$10^5$ JJ per $cm^2$. We suggest a few niche applications for this type of AC-biased circuits, not requiring high clock rates. E.g., these, scalable to millions of JJs per chip, circuits can serve as a convenient benchmark for new SFQ fabrication technology nodes, allowing the operating margins of individual cells to be extracted and, thus, 'visualize' individual fabrication defects and flux trapping events. The circuit can also be developed into a mega-pixel imaging array for a magnetic field microscope.

cond-mat.supr-con↗

arXiv2005

Rapid Ballistic Readout for Flux Qubits

We suggest a new type of the magnetic flux detector which can be optimized with respect to the measurement back-action, e.g. for the situation of quantum measurements. The detector is based on manipulation of ballistic motion of individual fluxons in a Josephson transmission line (JTL), with the output information contained in either probabilities of fluxon transmission/reflection, or time delay associated with the fluxon propagation through the JTL. We calculate the detector characteristics of the JTL and derive equations for conditional evolution of the measured system both in the transmission/reflection and the time-delay regimes. Combination of the quantum-limited detection with control over individual fluxons should make the JTL detector suitable for implementation of non-trivial quantum measurement strategies, including conditional measurements and feedback control schemes.

cond-mat.mes-hall↗