arXiv subjects

Veeresh Deshpande

Publications and source records attributed to Veeresh Deshpande.

13 recordsLinked to original sources

arXiv2026

In-Substrate Imaging of Diamond hBN FET Current via Widefield Quantum Diamond Microscopy

We demonstrate widefield magnetic imaging of current flow in hydrogen terminated diamond field effect transistors (FETs) through in-substrate nitrogen vacancy (NV) centers. Hydrogen termination of the diamond surface induces a two dimensional hole gas (2DHG), while an ensemble of near surface NV centers located $ \sim 1~\mu m$ below the surface enables noninvasive magnetic imaging of current flow with micrometer scale spatial resolution. The FETs were electrically characterized over a range of drain source biases $V_{ds}= 0$ to $-15V$ and gate voltages,$V_{gs}= +3$ to $-9V$ followed by in situ widefield NV magnetometry during device operation. Magnetic field maps and reconstructed current density distributions directly visualize current injection at the source drain contacts and transport beneath the hBN gated channel. Magnetic field maps reveal current density variations in the channel region owing to non-uniformities or defects in the gate dielectric. In addition, we observe a pronounced enhancement of the drain current ($\sim 600-900 \mu A$) and a shift in the apparent threshold voltage during laser illumination, reflecting photo induced changes in channel electrostatics. By correlating gate dependent magnetic images with simultaneous electrical measurements, we directly link spatial current distributions to FET transfer characteristics, providing new insight into buried interface transport and non-uniform gating effects in the transistor channel. As the methodology is compatible with top gated FETs, it can be used to map channel current distributions with micrometer resolution in emerging channel materials, such as 2D materials and wide bandgap channels, and establish widefield NV magnetometry as a powerful platform for probing charge transport in transistors and Van der Waals dielectric heterostructures.

cond-mat.mes-hall↗

arXiv2025

Defect-Aware Physics-Based Compact Model for Ferroelectric nvCap: From TCAD Calibration to Circuit Co-Design

Ferroelectric non-volatile capacitance-based memories enable non-destructive readout and low-power in-memory computing with 3D stacking potential. However, their limited memory window (1-10 fF/{\mu}m) requires material-device-circuit co-optimization. Existing compact models fail to capture the physics of small-signal capacitance, device variability, and cycling degradation, which are critical parameters for circuit design. In non-volatile capacitance devices, the small-signal capacitance difference of the polarization states is the key metric. The majority of the reported compact models do not incorporate any physical model of the capacitance as a function of voltage and polarization. We present a physics-based compact model that captures small-signal capacitance, interface and bulk defect contributions, and device variations through multi-scale modeling combining experimental data, TCAD simulations, and circuit validation. Based on this methodology, we show optimized memory read-out with +/- 5 mV sense margin and impact of device endurance at the circuit level. This work presents a comprehensive compact model which enables the design of selector-less arrays and 3D-stacked memories for compute-in-memory and storage memory.

cs.ET↗

arXiv2025

Symbol Detection in a MIMO Wireless Communication System Using a FeFET-coupled CMOS Ring Oscillator Array

Symbol decoding in multiple-input multiple-output (MIMO) wireless communication systems requires the deployment of fast, energy-efficient computing hardware deployable at the edge. The brute-force, exact maximum likelihood (ML) decoder, solved on conventional classical digital hardware, has exponential time complexity. Approximate classical solvers implemented on the same hardware have polynomial time complexity at the best. In this article, we design an alternative ring-oscillator-based coupled oscillator array to act as an oscillator Ising machine (OIM) and heuristically solve the ML-based MIMO detection problem. Complementary metal oxide semiconductor (CMOS) technology is used to design the ring oscillators, and ferroelectric field effect transistor (FeFET) technology is chosen as the coupling element (X) between the oscillators in this CMOS + X OIM design. For this purpose, we experimentally report high linear range of conductance variation (1 micro-S to 60 micro-S) in a FeFET device fabricated at 28 nm high-K/ metal gate (HKMG) CMOS technology node. We incorporate the conductance modulation characteristic in SPICE simulation of the ring oscillators connected in an all-to-all fashion through a crossbar array of these FeFET devices. We show that the above range of conductance variation of the FeFET device is suitable to obtain optimum OIM performance with no significant performance drop up to a MIMO size of 100 transmitting and 100 receiving antennas, thereby making FeFET a suitable device for this application. Our simulations and associated analysis using the Kuramoto model of oscillators also predict that this designed classical analog OIM, if implemented experimentally, will offer logarithmic scaling of computation time with MIMO size, thereby offering a huge improvement (in terms of computation speed) over aforementioned MIMO decoders run on conventional digital hardware.

physics.app-ph↗

arXiv2024

Heracles: A HfO2 Ferroelectric Capacitor Compact Model for Efficient Circuit Simulations

The growing use of ferroelectric-based technology, extending beyond conventional memory storage applications, necessitates the development of compact models that can be easily integrated into circuit simulation environments. These models assist circuit designers in the design and the early assessment of the performance of their systems. The Heracles model is a physics-based compact model for circuit simulations in a SPICE environment for HfO2-based ferroelectric capacitors (FeCaps). The model has been calibrated based on experimental data obtained from HfO2-based FeCaps. A thermal model with an accurate description of the device parasitics is included to derive precise device characteristics based on first principles. The incorporation of statistical device data enables Monte Carlo analysis based on realistic distributions, thereby rendering the model particularly well-suited for design-technology co-optimization (DTCO). The model's efficacy is further demonstrated in circuit simulations using an integrated circuit with current programming, wherein partial switching of the ferroelectric polarization is observed. Finally, the model was benchmarked in an array simulation, reaching convergence in 1.8 s with an array size of 100 kb.

cs.ET↗

arXiv2023

Design Space and Variability Analysis of SOI MOSFET for Ultra-Low Power Band-to-Band Tunneling Neurons

Large spiking neural networks (SNNs) require ultra-low power and low variability hardware for neuromorphic computing applications. Recently, a band-to-band tunneling-based (BTBT) integrator, enabling sub-kHz operation of neurons with area and energy efficiency, was proposed. For an ultra-low power implementation of such neurons, a very low BTBT current is needed, so minimizing current without degrading neuronal properties is essential. Low variability is needed in the ultra-low current integrator to avoid network performance degradation in a large BTBT neuron-based SNN. To address this, we conducted design space and variability analysis in TCAD, utilizing a well-calibrated TCAD deck with experimental data from GlobalFoundries 32nm PD-SOI MOSFET. First, we discuss the physics-based explanation of the tunneling mechanism. Second, we explore the impact of device design parameters on SOI MOSFET performance, highlighting parameter sensitivities to tunneling current. With device parameters' optimization, we demonstrate a ~20x reduction in BTBT current compared to the experimental data. Finally, a variability analysis that includes the effects of random dopant fluctuations (RDF), oxide thickness variability (OTV), and channel-oxide interface traps DIT in the BTBT, SS, and ON regimes of operation is shown. The BTBT regime shows high sensitivity to the RDF and OTV as any variation in them directly modulates the tunnel length or the electric field at the drain-channel junction, whereas minimal sensitivity to DIT is observed.

physics.app-ph↗

arXiv2023

Ferroelectric MirrorBit-Integrated Field-Programmable Memory Array for TCAM, Storage, and In-Memory Computing Applications

In-memory computing on a reconfigurable architecture is the emerging field which performs an application-based resource allocation for computational efficiency and energy optimization. In this work, we propose a Ferroelectric MirrorBit-integrated field-programmable reconfigurable memory. We show the conventional 1-Bit FeFET, the MirrorBit, and MirrorBit-based Ternary Content-addressable memory (MCAM or MirrorBit-based TCAM) within the same field-programmable array. Apart from the conventional uniform Up and Down polarization states, the additional states in the MirrorBit are programmed by applying a non-uniform electric field along the transverse direction, which produces a gradient in the polarization and the conduction band energy. This creates two additional states, thereby, creating a total of 4 states or 2-bit of information. The gradient in the conduction band resembles a Schottky barrier (Schottky diode), whose orientation can be configured by applying an appropriate field. The TCAM operation is demonstrated using the MirrorBit-based diode on the reconfigurable array. The reconfigurable array architecture can switch from AND-type to NOR-type and vice-versa. The AND-type array is appropriate for programming the conventional bit and the MirrorBit. The MirrorBit-based Schottky diode in the NOR-array resembles a crossbar structure, which is appropriate for diode-based CAM operation. Our proposed memory system can enable fast write via 1-bit FeFET, the dense data storage capability by Mirror-bit technology and the fast search capability of the MCAM. Further, the dual configurability enables power, area and speed optimization making the reconfigurable Fe-Mirrorbit memory a compelling solution for In-memory and associative computing.

eess.SY↗

arXiv2023

Sub-10 nm Probing of Ferroelectricity in Heterogeneous Materials by Machine Learning Enabled Contact Kelvin Probe Force Microscopy

Reducing the dimensions of ferroelectric materials down to the nanoscale has strong implications on the ferroelectric polarization pattern and on the ability to switch the polarization. As the size of ferroelectric domains shrinks to nanometer scale, the heterogeneity of the polarization pattern becomes increasingly pronounced, enabling a large variety of possible polar textures in nanocrystalline and nanocomposite materials. Critical to the understanding of fundamental physics of such materials and hence their applications in electronic nanodevices, is the ability to investigate their ferroelectric polarization at the nanoscale in a non-destructive way. We show that contact Kelvin probe force microscopy (cKPFM) combined with a k-means response clustering algorithm enables to measure the ferroelectric response at a mapping resolution of 8 nm. In a BaTiO3 thin film on silicon composed of tetragonal and hexagonal nanocrystals, we determine a nanoscale lateral distribution of discrete ferroelectric response clusters, fully consistent with the nanostructure determined by transmission electron microscopy. Moreover, we apply this data clustering method to the cKPFM responses measured at different temperatures, which allows us to follow the corresponding change in polarization pattern as the Curie temperature is approached and across the phase transition. This work opens up perspectives for mapping complex ferroelectric polarization textures such as curled/swirled polar textures that can be stabilized in epitaxial heterostructures and more generally mapping the polar domain distribution of any spatially-highly-heterogeneous ferroelectric materials.

cond-mat.mtrl-sci↗

arXiv2022

A Ferroelectric Tunnel Junction-based Integrate-and-Fire Neuron

Event-based neuromorphic systems provide a low-power solution by using artificial neurons and synapses to process data asynchronously in the form of spikes. Ferroelectric Tunnel Junctions (FTJs) are ultra low-power memory devices and are well-suited to be integrated in these systems. Here, we present a hybrid FTJ-CMOS Integrate-and-Fire neuron which constitutes a fundamental building block for new-generation neuromorphic networks for edge computing. We demonstrate electrically tunable neural dynamics achievable by tuning the switching of the FTJ device.

cs.ET↗

arXiv2022

Insights on the variability of Cu filament formation in the SiO2 electrolyte of quantized-conductance conductive bridge random access memory devices

Conductive bridge random access memory devices such as Cu/SiO2/W are promising candidates for applications in neuromorphic computing due to their fast, low-voltage switching, multiple-conductance states, scalability, low off-current, and full compatibility with advanced Si CMOS technologies. The conductance states, which can be quantized, originate from the formation of a Cu filament in the SiO2 electrolyte due to cation-migration-based electrochemical processes. A major challenge related to the filamentary nature is the strong variability of the voltage required to switch the device to its conducting state. Here, based on a statistical analysis of more than hundred fifty Cu/SiO2/W devices, we point to the key role of the activation energy distribution for copper ion diffusion in the amorphous SiO2. The cycle-to-cycle variability is modeled well when considering the theoretical energy landscape for Cu diffusion paths to grow the filament. Perspectives of this work point to developing strategies to narrow the distribution of activation energies in amorphous SiO2.

cond-mat.mtrl-sci↗

arXiv2021

CMOS back-end-of-line compatible ferroelectric tunnel junction devices

Ferroelectric tunnel junction devices based on ferroelectric thin films of solid solutions of hafnium dioxide can enable CMOS integration of ultra-low power ferroelectric devices with potential for memory and emerging computing schemes such as in-memory computing and neuromorphic applications. In this work, we present ferroelectric tunnel junctions based on Hf$_{0.5}$Zr$_{0.5}$O$_{2}$ with materials and processes compatible with CMOS back-end-of-line integration. We show a device architecture based on W-Hf$_{0.5}$Zr$_{0.5}$O$_{2}$-Al$_{2}$O$_{3}$-TiN stacks featuring low temperature annealing at 400°C with performance comparable to those obtained with higher temperature annealing conditions.

physics.app-ph↗

arXiv2020

Silicon quantum dot devices with a self-aligned second gate layer

We implement silicon quantum dot devices with two layers of gate electrodes using a self-alignment technique, which allows for ultra-small gate lengths and intrinsically perfect layer-to-layer alignment. In a double quantum dot system, we investigate hole transport and observe current rectification due to Pauli spin blockade. Magnetic field measurements indicate that hole spin relaxation is dominated by spin-orbit interaction, and enable us to determine the effective hole $g$-factor $\simeq1.6$. From an avoided singlet-triplet crossing, occurring at high magnetic field, the spin-orbit coupling strength $\simeq0.27$meV is obtained, promising fast and all-electrical spin control.

cond-mat.mes-hall↗

arXiv2018

Ambipolar quantum dots in undoped silicon fin field-effect transistors

We integrate ambipolar quantum dots in silicon fin field-effect transistors using exclusively standard complementary metal-oxide-semiconductor fabrication techniques. We realize ambipolarity by replacing conventional highly-doped source and drain electrodes by a metallic nickel silicide with Fermi level close to the silicon mid-gap position. Such devices operate in a dual mode, either as classical field-effect or single-electron transistor. We implement a classical logic NOT gate at low temperature by tuning two interconnected transistors into opposite polarities. In the quantum regime, we demonstrate stable quantum dot operation in the few charge carrier Coulomb blockade regime for both electrons and holes.

cond-mat.mes-hall↗

arXiv2012

A tunable, dual mode field-effect or single electron transistor

A dual mode device behaving either as a field-effect transistor or a single electron transistor (SET) has been fabricated using silicon-on-insulator metal oxide semiconductor technology. Depending on the back gate polarisation, an electron island is accumulated under the front gate of the device (SET regime), or a field-effect transistor is obtained by pinching off a bottom channel with a negative front gate voltage. The gradual transition between these two cases is observed. This dual function uses both vertical and horizontal tunable potential gradients in non-overlapped silicon-on-insulator channel.

cond-mat.mes-hall↗