arXiv subjects

Virginia N. Ciriano-Tejel

Publications and source records attributed to Virginia N. Ciriano-Tejel.

3 recordsLinked to original sources

arXiv2025

Electrical readout of spins in the absence of spin blockade

In semiconductor nanostructures, spin blockade (SB) is the most scalable mechanism for electrical spin readout, requiring only two bound spins for its implementation. In conjunction with charge sensing techniques, SB has led to high-fidelity readout of spins in semiconductor-based quantum processors. However, various mechanisms may lift SB, such as strong spin-orbit coupling (SOC) or low-lying excited states, hence posing challenges to perform spin readout at scale and with high fidelity in such systems. Here, we present a method, based on the dependence of the two-spin system polarizability on energy detuning, to perform spin state readout even when SB lifting mechanisms are dominant. It leverages SB lifting as a resource to detect selectively different spin measurement outcomes. We demonstrate the method using a hybrid system formed by a quantum dot (QD) and a Boron acceptor in a silicon p-type transistor and show spin-selective readout of different spin states under SB lifting conditions due to (i) SOC and (ii) low-lying orbital states in the QD. We further use the method to determine the detuning-dependent spin relaxation time of 0.1 - 8 $μ$s. Our method should help perform projective spin measurements with high spin-to-charge conversion fidelity in systems subject to strong SOC, will facilitate state leakage detection and enable complete readout of two-spin states.

cond-mat.mes-hall↗

arXiv2025

Large-scale characterization of Single-Hole Transistors in 22-nm FDSOI CMOS Technology

State-of-the-art quantum processors have recently grown to reach 100s of physical qubits. As the number of qubits continues to grow, new challenges associated with scaling arise, such as device variability reduction and integration with cryogenic electronics for I/O management. Spin qubits in silicon quantum dots provide a platform where these problems may be mitigated, having demonstrated high control and readout fidelities and compatibility with large-scale manufacturing techniques of the semiconductor industry. Here, we demonstrate the monolithic integration of 384 p-type quantum dots, each embedded in a silicon transistor, with on-chip digital and analog electronics, all operating at deep cryogenic temperatures. The chip is fabricated using 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. We extract key quantum dot parameters by fast readout and automated machine learning routines to determine the link between device dimensions and quantum dot yield, variability, and charge noise figures. Overall, our results demonstrate a path to monolithic integration of quantum and classical electronics at scale.

cond-mat.mes-hall↗

arXiv2023

Rapid cryogenic characterisation of 1024 integrated silicon quantum dots

Quantum computers are nearing the thousand qubit mark, with the current focus on scaling to improve computational performance. As quantum processors grow in complexity, new challenges arise such as the management of device variability and the interface with supporting electronics. Spin qubits in silicon quantum dots are poised to address these challenges with their proven control fidelities and potential for compatibility with large-scale integration. Here, we demonstrate the integration of 1024 silicon quantum dots with on-chip digital and analogue electronics, all operating below 1 K. A high-frequency analogue multiplexer provides fast access to all devices with minimal electrical connections, enabling characteristic data across the quantum dot array to be acquired in just 5 minutes. We achieve this by leveraging radio-frequency reflectometry with state-of-the-art signal integrity, reaching a minimum integration time of 160 ps. Key quantum dot parameters are extracted by fast automated machine learning routines to assess quantum dot yield and understand the impact of device design. We find correlations between quantum dot parameters and room temperature transistor behaviour that may be used as a proxy for in-line process monitoring. Our results show how rapid large-scale studies of silicon quantum devices can be performed at lower temperatures and measurement rates orders of magnitude faster than current probing techniques, and form a platform for the future on-chip addressing of large scale qubit arrays.

quant-ph↗