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Vitor Silva

Publications and source records attributed to Vitor Silva.

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GPU-Accelerated Syndrome Decoding for Quantum LDPC Codes below the 63 $\mu$s Latency Threshold

This paper presents a GPU-accelerated decoder for quantum low-density parity-check (QLDPC) codes that achieves sub-$63$ $\mu$s latency, below the surface code decoder's real-time threshold demonstrated on Google's Willow quantum processor. While surface codes have demonstrated below-threshold performance, the encoding rates approach zero as code distances increase, posing challenges for scalability. Recently proposed QLDPC codes, such as those by Panteleev and Kalachev, offer constant-rate encoding and asymptotic goodness but introduce higher decoding complexity. To address such limitation, this work presents a parallelized belief propagation decoder leveraging syndrome information on commodity GPU hardware. Parallelism was exploited to maximize performance within the limits of target latency, allowing decoding latencies under $50$ $\mu$s for [[$784$, $24$, $24$]] codes and as low as $23.3$ $\mu$s for smaller codes, meeting the tight timing constraints of superconducting qubit cycles. These results show that real-time, scalable decoding of asymptotically good quantum codes is achievable using widely available commodity hardware, advancing the feasibility of fault-tolerant quantum computation beyond surface codes.

quant-ph

An Experimental Exploration of In-Memory Computing for Multi-Layer Perceptrons

In modern computer architectures, the performance of many memory-bound workloads (e.g., machine learning, graph processing, databases) is limited by the data movement bottleneck that emerges when transferring large amounts of data between the main memory and the central processing unit (CPU). Processing-in-memory is an emerging computing paradigm that aims to alleviate this data movement bottleneck by performing computation close to or within the memory units, where data resides. One example of a prevalent workload whose performance is bound by the data movement bottleneck is the training and inference process of artificial neural networks. In this work, we analyze the potential of modern general-purpose PiM architectures to accelerate neural networks. To this end, we selected the UPMEM PiM system, the first commercially available real-world general-purpose PiM architecture. We compared the implementation of multilayer perceptrons (MLPs) in PiM with a sequential baseline running on an Intel Xeon CPU. The UPMEM implementation achieves up to $259\times$ better performance for inference of large batch sizes when compared against the CPU that exploits the size of the available PiM memory. Additionally, two smaller MLPs were implemented using UPMEM's working SRAM (WRAM), a scratchpad memory, to evaluate their performance against a low-power Nvidia Jetson graphics processing unit (GPU), providing further insights into the efficiency of UPMEM's PiM for neural network inference. Results show that using WRAM achieves kernel execution times for MLP inference of under $3$ ms, which is within the same order of magnitude as low-power GPUs.

cs.DC

In-Memory Non-Binary LDPC Decoding

Low-density parity-check (LDPC) codes are an important feature of several communication and storage applications, offering a flexible and effective method for error correction. These codes are computationally complex and require the exploitation of parallel processing to meet real-time constraints. As advancements in arithmetic and logic unit technology allowed for higher performance of computing systems, memory technology has not kept the same pace of development, creating a data movement bottleneck and affecting parallel processing systems more dramatically. To alleviate the severity of this bottleneck, several solutions have been proposed, namely the processing in-memory (PiM) paradigm that involves the design of compute units to where (or near) the data is stored, utilizing thousands of low-complexity processing units to perform out bit-wise and simple arithmetic operations. This paper presents a novel efficient solution for near-memory non-binary LDPC decoders in the UPMEM system, for the best of our knowledge the first real hardware PiM-based non-binary LDPC decoder that is benchmarked against low-power GPU parallel solutions highly optimized for throughput performance. PiM-based non-binary LDPC decoders can achieve 76 Mbit/s of decoding throughput, which is even competitive when compared against implementations running in edge GPUs.

cs.DC

Streamlined Swift Allocation Strategies for Radio Stripe Networks

This paper proposes the use of an access point (AP) selection scheme to improve the total uplink (UL) spectral efficiency (SE) of a radio stripe (RS) network. This scheme optimizes the allocation matrix between the total number of APs' antennas and users' equipment (UEs) while considering two state-of-the-art and two newly proposed equalization approaches: centralized maximum ratio combining (CMRC), centralized optimal sequence linear processing (COSLP), sequential MRC (SMRC), and parallel MRC (PMRC). The optimization problem is solved through a low-complexity and adaptive genetic algorithm (GA) which aims to output an efficient solution for the AP-UE association matrix. We evaluate the proposed schemes in several network scenarios in terms of SE performance, convergence speed, computational complexity, and fronthaul signalling capacity requirements. The COSLP exhibits the best SE performance at the expense of high computational complexity and fronthaul signalling. The SMRC and PMRC are efficient solutions alternatives to the CMRC, improving its computational complexity and convergence speed. Additionally, we assess the adaptability of the MRC schemes for two different instances of network change: when a new randomly located UE must connect to the RS network and when a random UE is removed from it. We have found that in some cases, by reusing the allocation matrix from the original instance as an initial solution, the SMRC and/or the PMRC can significantly boost the optimization performance of the GA-based AP selection scheme.

eess.SP

4x2 Hot electron bolometer mixer arrays for detection at 1.46, 1.9 and 4.7 THz for a balloon borne terahertz observatory

We have demonstrated three 4x2 hot electron bolometer (HEB) mixer arrays for operation at local oscillator (LO) frequencies of 1.46, 1.9 and 4.7 THz, respectively. They consist of spiral antenna coupled NbN HEB mixers combined with elliptical lenses. These are to date the highest pixel count arrays using a quasi-optical coupling scheme at supra-THz frequencies. At 1.4 THz, we measured an average double sideband mixer noise temperature of 330 K, a mixer conversion loss of 5.7 dB, and an optimum LO power of 210 nW. The array at 1.9 THz has an average mixer noise temperature of 420K, a conversion loss of 6.9 dB, and an optimum LO power of 190 nW. For the array at 4.7 THz, we obtained an average mixer noise temperature of 700 K, a conversion loss of 9.7 dB, and an optimum LO power of 240 nW. We found the arrays to be uniform regarding the mixer noise temperature with a standard deviation of 3-4%, the conversion loss with a standard deviation of 7-10%, and optimum LO power with a standard deviation of 5-6%. The noise bandwidth was also measured, being 3.5 GHz for the three arrays. These performances are comparable to previously reported values in the literature for single pixels and also other detector arrays. Our arrays meet the requirements of the Galactic/Extra-Galactic ULDB Spectroscopic Terahertz Observatory (GUSTO), a NASA balloon borne observatory, and are therefore scheduled to fly as part of the payload, which is expected to be launched in December 2023.

physics.ins-det

Named Entity Recognition in Twitter: A Dataset and Analysis on Short-Term Temporal Shifts

Recent progress in language model pre-training has led to important improvements in Named Entity Recognition (NER). Nonetheless, this progress has been mainly tested in well-formatted documents such as news, Wikipedia, or scientific articles. In social media the landscape is different, in which it adds another layer of complexity due to its noisy and dynamic nature. In this paper, we focus on NER in Twitter, one of the largest social media platforms, and construct a new NER dataset, TweetNER7, which contains seven entity types annotated over 11,382 tweets from September 2019 to August 2021. The dataset was constructed by carefully distributing the tweets over time and taking representative trends as a basis. Along with the dataset, we provide a set of language model baselines and perform an analysis on the language model performance on the task, especially analyzing the impact of different time periods. In particular, we focus on three important temporal aspects in our analysis: short-term degradation of NER models over time, strategies to fine-tune a language model over different periods, and self-labeling as an alternative to lack of recently-labeled data. TweetNER7 is released publicly (https://huggingface.co/datasets/tner/tweetner7) along with the models fine-tuned on it.

cs.CL

Joint Channel Estimation and Synchronization Techniques for Time Interleaved Block Windowed Burst OFDM

From a conceptual perspective, 5G technology promises to deliver low latency, high data rate and more reliable connections for the next generations of communication systems. To face these demands, modulation schemes based on Orthogonal Frequency Domain Multiplexing (OFDM) can accommodate these requirements for wireless systems. On the other hand, several hybrid OFDM-based systems such as the Time-Interleaved Block Windowed Burst Orthogonal Frequency Division Multiplexing (TIBWB-OFDM) are capable of achieving even better spectral confinement and power efficiency. This paper addresses to the implementation of the TIBWB-OFDM system in a more realistic and practical wireless link scenarios by addressing the challenges of proper and reliable channel estimation and frame synchronization. We propose to incorporate a preamble formed by optimum correlation training sequences, such as the Zadoff-Chu (ZC) sequences. The added ZC preamble sequence is used to jointly estimate the frame beginning, through signal correlation strategies and a threshold decision device, and acquire the channel state information (CSI), by employing estimators based on the preamble sequence and the transmitted data. The employed receiver estimators show that it is possible to detect the TIBWB-OFDM frame beginning and provide a close BER performance comparatively to the one where the perfect channel is known.

eess.SP

Power Challenges of Large Scale Research Infrastructures: the Square Kilometer Array and Solar Energy Integration; Towards a zero-carbon footprint next generation telescope

The Square Kilometer Array (SKA) will be the largest Global science project of the next two decades. It will encompass a sensor network dedicated to radioastronomy, covering two continents. It will be constructed in remote areas of South Africa and Australia, spreading over 3000Km, in high solar irradiance latitudes. Solar Power supply is therefore an option to power supply the SKA and contribute to a zero carbon footprint next generation telescope. Here we outline the major characteristics of the SKA and some innovation approaches on thermal solar energy Integration with SKA prototypes.

astro-ph.IM