arXiv subjects

Vladimir Bolkhovsky

Publications and source records attributed to Vladimir Bolkhovsky.

16 recordsLinked to original sources

arXiv2023

Development of Self-Shunted Josephson Junctions For a Ten-Superconductor-Layer Fabrication Process: Nb/NbN$_x$/Nb Junctions

To increase integration scale of superconductor electronics, we are developing a new, SFQ7ee, node of the fabrication process at MIT Lincoln Laboratory. In comparison to the existing SFQ5ee node, we increased the number of fully planarized superconducting layers to ten and utilized NbN and NbN/Nb kinetic inductors to increase the inductor number density above 100 million per cm$^2$. Increasing the Josephson junction (JJ) number density to the same level requires implementing self-shunted high-$J_c$ JJs. We investigated properties of Nb/NbN$_x$/Nb trilayer JJs as a potential replacement of high-$J_c$ Nb/Al-AlO$_x$/Nb JJs, where NbN$_x$ is a disordered, nonsuperconducting nitride deposited by reactive sputtering. Dependences of the $I_cR_n$ product and Josephson critical current density, $J_c$ on the NbN$_x$ barrier thickness and on temperature were studied in the thickness range from 5 nm to 20 nm. The fabricated JJs can be described by the microscopic theory of SNS junctions, assuming no suppression of the energy gap in Nb electrodes near the NbN$_x$ interfaces and a Cooper pair decay length in the NbN$_x$ barrier of about 2.3 nm. Current-voltage characteristics of the JJs are well described by the RCSJ model. In the studied range $J_c$ < 10 mA/$μ$$m^2$, the Nb/NbN$_x$/Nb JJs have lower specific resistance $R_nA$, lower $I_cR_n$ product, and a stronger dependence of the $I_cR_n$ on temperature than self-shunted or critically damped externally shunted Nb/Al-AlO$_x$/Nb JJs with the same critical current density; here $A$ is the JJ area, $R_n$ the JJ effective shunting resistance.

cond-mat.supr-con↗

arXiv2023

Extremely Large Area (88 mm X 88 mm) Superconducting Integrated Circuit (ELASIC)

Superconducting integrated circuit (SIC) is a promising "beyond-CMOS" device technology enables speed-of-light, nearly lossless communications to advance cryogenic (4 K or lower) computing. However, the lack of large-area superconducting IC has hindered the development of scalable practical systems. Herein, we describe a novel approach to interconnect 16 high-resolution deep UV (DUV EX4, 248 nm lithography) full reticle circuits to fabricate an extremely large (88mm X 88 mm) area superconducting integrated circuit (ELASIC). The fabrication process starts by interconnecting four high-resolution DUV EX4 (22 mm X 22 mm) full reticles using a single large-field (44 mm X 44 mm) I-line (365 nm lithography) reticle, followed by I-line reticle stitching at the boundaries of 44 mm X 44 mm fields to fabricate the complete ELASIC field (88 mm X 88 mm). The ELASIC demonstrated a 2X-12X reduction in circuit features and maintained high-stitched line superconducting critical currents. We examined quantum flux parametron (QFP) circuits to demonstrate the viability of common active components used for data buffering and transmission. Considering that no stitching requirement for high-resolution EX4 DUV reticles is employed, the present fabrication process has the potential to advance the scaling of superconducting quantum devices.

cond-mat.supr-con↗

arXiv2023

Broadband Squeezed Microwaves and Amplification with a Josephson Traveling-Wave Parametric Amplifier

Squeezing of the electromagnetic vacuum is an essential metrological technique used to reduce quantum noise in applications spanning gravitational wave detection, biological microscopy, and quantum information science. In superconducting circuits, the resonator-based Josephson-junction parametric amplifiers conventionally used to generate squeezed microwaves are constrained by a narrow bandwidth and low dynamic range. In this work, we develop a dual-pump, broadband Josephson traveling-wave parametric amplifier that combines a phase-sensitive extinction ratio of 56 dB with single-mode squeezing on par with the best resonator-based squeezers. We also demonstrate two-mode squeezing at microwave frequencies with bandwidth in the gigahertz range that is almost two orders of magnitude wider than that of contemporary resonator-based squeezers. Our amplifier is capable of simultaneously creating entangled microwave photon pairs with large frequency separation, with potential applications including high-fidelity qubit readout, quantum illumination and teleportation.

quant-ph↗

arXiv2023

Progress toward superconductor electronics fabrication process with planarized NbN and NbN/Nb layers

To increase density of superconductor digital and neuromorphic circuits by 10x and reach integration scale of $10^8$ Josephson junctions (JJs) per chip, we developed a new fabrication process on 200-mm wafers, using self-shunted Nb/Al-AlOx/Nb JJs and kinetic inductors. The process has a layer of JJs, a layer of resistors, and 10 fully planarized superconducting layers: 8 Nb layers and 2 layers of high kinetic inductance materials, Mo$_2$N and NbN, with sheet inductance of 8 pH/sq and 3 pH/sq, respectively. NbN films were deposited by two methods: with $T_c$=15.5 K by reactive sputtering of a Nb target in Ar+N$_2$ mixture; with $T_c$ in the range from 9 K to 13 K by plasma-enhanced chemical vapor deposition (PECVD) using Tris(diethylamido)(tert-butylimido)niobium(V) metalorganic precursor. PECVD of NbN was investigated to obtain conformal deposition and filling narrow trenches and vias with high depth-to-width ratios, which was not possible to achieve using sputtering and other physical vapor deposition (PVD) methods at temperatures below $200 ^oC$ required to prevent degradation of Nb/Al-AlOx/Nb junctions. Nb layers with 200 nm thickness are used in the process layer stack as ground planes to maintain a high level of interlayer shielding and low intralayer mutual coupling, for passive transmission lines with wave impedances matching impedances of JJs, typically <=50 $Ω$, and for low-value inductors. NbN and NbN/Nb bilayer are used for cell inductors. Using NbN/Nb bilayers and individual pattering of both layers to form inductors allowed us to minimize parasitic kinetic inductance associated with interlayer vias and connections to JJs as well as to increase critical currents of the vias. Fabrication details and results of electrical characterization of NbN films, wires, and vias, and comparison with Nb properties are given.

cond-mat.supr-con↗

arXiv2023

Self- and Mutual Inductance of NbN and Bilayer NbN/Nb Inductors in Planarized Fabrication Process With Nb Ground Planes

We present measurements of the self- and mutual inductance of NbN and bilayer NbN/Nb inductors with Nb ground plane(s) fabricated in an advanced process for superconductor electronics developed at MIT Lincoln Laboratory. In this process, the signal traces of logic cell inductors are made either of a 200-nm NbN layer with $T_c$=15 K or of an in-situ deposited NbN/Nb bilayer, replacing a 200-nm Nb layer M6 in the standard SFQ5ee process with nine superconducting layers. Nb ground planes were preserved to maintain a high level of interlayer shielding and low intralayer mutual coupling. A two-step patterning of the top Nb and the bottom NbN layers of the NbN/Nb bilayer allows to create inductors in a very wide range of linear inductance values, from low values ~ 0.4 pH/$μ$m typical for Nb geometrical inductors to ~ 35 pH/$μ$m typical to thin-film kinetic inductors. Mutual inductance of NbN and Nb inductors, of NbN inductors, and of bilayer inductors is the same as between two Nb inductors with the same geometry and placement between the ground planes, i.e., mutual inductance does not depend on superconducting properties of the signal traces in the studied range of linewidths. We measured magnetic field penetration depth and kinetic inductance of NbN films with thickness t=200 nm to be $λ$ = 491+/-5 nm and 1.51 pH/sq, and 2.06 pH/sq at t=150 nm. The kinetic inductance was found to be larger than that expected for superconductors with short mean free path, indicating a reduction in the superfluid density, likely due to carrier localization effects. Kinetic inductance associated with right-angled bends of the NbN inductors is negligible at linewidths $w<λ^2/t$, indicating a very small current crowding in structures with superconducting ground plane(s). Implementation of NbN and NbN/Nb inductors can significantly increase integration scale of superconductor digital electronics.

cond-mat.supr-con↗

arXiv2021

Mutual and self-inductance in planarized multilayered superconductor integrated circuits: Microstrips, striplines, bends, meanders, ground plane perforations

Data are presented on mutual and self-inductance of various inductors used in multilayered superconductor integrated circuits: microstrips and striplines with widths of signal traces from 250 nm to a few micrometers, located on the same circuit layer at various distances from each other (from 250 nm to a few micrometers) and/or on different layers spaced vertically; effect of long slits in the ground plane(s) along the inductors on their mutual inductance; inductance of right-angled bends; inductance of meanders. Simple analytical expressions for mutual and self-inductance of the basic inductors are given, describing experimental data with accuracy better than 2% in a very wide range of parameters. They can be used for superconductor integrated circuit design and calibration of numerical inductance extractors. Measurements were done using circuits fabricated in fully planarized fabrication processes with eight niobium layers and Nb/Al-AlOx/Nb Josephson junctions, known as the SFQ5ee and SC1 processes developed at MIT Lincoln Laboratory for superconductor electronics. Mutual inductance decreases exponentially with distance between striplines and as a second power of the distance between microstrips, strongly depends on magnetic field penetration depths in superconducting ground planes, whereas superconducting properties of the signal traces are practically immaterial. Weak dependence of mutual inductance on the linewidth of superconducting wires indicates that area of superconducting flux transformers - the essential component of all digital circuits using ac power, superconducting qubits, and sensor arrays - scales poorly with the linewidth, putting a predictable upper limit on the integration scale of such circuits.

cond-mat.supr-con↗

arXiv2021

Inductance and mutual inductance of superconductor integrated circuit features with sizes down to 120 nm. Part I

Data are presented on inductance of various features used in superconductor digital integrated circuits such as microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers and composite vias between distant superconducting layers. Effects of magnetic flux trapping in ground plane moats on coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations. Test circuits used for the measurements were fabricated in a new 150-nm node of a fully planarized process with eight niobium layers, SC2 process, developed at MIT Lincoln Laboratory for superconductor electronics and in its 250-nm node SC1, as well as in the standard fabrication process SFQ5ee. The SC2 process utilizes 193-nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. All other processes use 248 nm photolithography. Effects of variation of process parameters on circuit inductors are discussed. The measured data are compared with the results of inductance extraction using software packages InductEx and wxLC. Part II is devoted to mutual inductance of various closely spaced features in integrated circuits, meanders, and transformers.

cond-mat.supr-con↗

arXiv2019

Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS π-Junctions

We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions in a fully planarized multilayer process on 200-mm wafers. The two junction layers can be, e.g., conventional Superconductor-Insulator-Superconductor (SIS) Nb/Al/AlO_x/Nb junctions with the same or different Josephson critical current densities, J_c. The process also allows integration of high-J_c Superconductor-Ferromagnet-Superconductor (SFS) or SFS'S JJs on the first junction layer with Nb/Al/AlO_x/Nb trilayer junctions on the second junction layer, or vice versa. In the present node, the SFS trilayer, Nb/Ni/Nb is placed below the standard SIS trilayer and separated by one niobium wiring layer. The main purpose of integrating the SFS and SIS junction layers is to provide compact π-phase shifters in logic cells of superconductor digital circuits and random access memories, and thereby increase the integration scale and functional density of superconductor electronics. The current node of the two-junction-layer process has six planarized niobium layers, two layers of resistors, and 350-nm minimum feature size. The target Josephson critical current densities for the SIS junctions are 100 μA/μm^2 and 200 μA/μm^2. We present the salient features of the new process, fabrication details, and characterization results on two layers of Josephson junctions integrated into one process, both for the conventional and π-junctions.

cond-mat.supr-con↗

arXiv2018

Superconductor Electronics Fabrication Process with MoN$_x$ Kinetic Inductors and Self-Shunted Josephson Junctions

Recent progress in superconductor electronics fabrication has enabled single-flux-quantum (SFQ) digital circuits with close to one million Josephson junctions (JJs) on 1-cm$^2$ chips. Increasing the integration scale further is challenging because of the large area of SFQ logic cells, mainly determined by the area of resistively shunted Nb/AlO$_x$-Al/Nb JJs and geometrical inductors utilizing multiple layers of Nb. To overcome these challenges, we are developing a fabrication process with self-shunted high-J$_c$ JJs and compact thin-film MoN$_x$ kinetic inductors instead of geometrical inductors. We present fabrication details and properties of MoN$_x$ films with a wide range of T$_c$, including residual stress, electrical resistivity, critical current, and magnetic field penetration depth λ$_0$. As kinetic inductors, we implemented Mo$_2$N films with T$_c$ about 8 K, λ$_0$ about 0.51 μm, and inductance adjustable in the range from 2 to 8 pH/sq. We also present data on fabrication and electrical characterization of Nb-based self-shunted JJs with AlO$_x$ tunnel barriers and J$_c$ = 0.6 mA/μm$^2$, and with 10-nm thick Si$_{1-x}$Nb$_x$ barriers, with x from 0.03 to 0.15, fabricated on 200-mm wafers by co-sputtering. We demonstrate that the electron transport mechanism in Si$_{1-x}$Nb$_x$ barriers at x < 0.08 is inelastic resonant tunneling via chains of multiple localized states. At larger x, their Josephson characteristics are strongly dependent on x and residual stress in Nb electrodes, and in general are inferior to AlO$_x$ tunnel barriers.

cond-mat.supr-con↗

arXiv2017

Developments Toward a 250-nm, Fully Planarized Fabrication Process With Ten Superconducting Layers And Self-Shunted Josephson Junctions

We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 μm made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity.

cond-mat.supr-con↗

arXiv2017

Properties of Unshunted and Resistively Shunted Nb/AlOx-Al/Nb Josephson Junctions With Critical Current Densities from 0.1 mA/μm^2 to 1 mA/μm^2

We investigated current-voltage characteristics of unshunted and externally shunted Josephson junctions (JJs) with high critical current densities, Jc, in order to extract their basic parameters and statistical characteristics for JJ modeling in superconducting integrated circuits and to assess their potential for future technology nodes. Nb/AlOx-Al/Nb JJs with diameters from 0.5 μm to 6 μm were fabricated using a fully planarized process with Mo or MoNx thin-film shunt resistors with sheet resistance Rsq = 2 Ω/sq and Rsq = 6 Ω/sq, respectively. We used our standard MIT LL process SFQ5ee to fabricate JJs with Jc = 0.1 mA/μm^2 and our new process SFQ5hs to make JJs with Jc = 0.2 mA/μm^2 and higher current densities up to about 1 mA/μm^2. Using LRC resonance features on the I-V characteristics of shunted JJs, we extract the inductance associated with molybdenum shunt resistors of 1.4 pH/sq. The main part this inductance, about 1.1 pH/sq, is the inductance of the 40-nm Mo resistor film, while the geometrical inductance of superconducting Nb wiring contributes the rest. We attribute this large inductance to kinetic inductance arising from the complex conductivity of a thin normal-metal film in an electromagnetic field with angular frequency ω, σ(ω)=σ0/(1+iωτ), where σ0 is the static conductivity and τ the electron scattering time. Using a resonance in a large-area unshunted high-Jc junction excited by a resistively coupled small-area shunted JJ, we extract the Josephson plasma frequency and specific capacitance of high-Jc junctions in 0.1 to 1 mA/μm^2 Jc range. We also present data on Jc targeting and JJ critical current spreads. We discuss using 0.2-mA/μm^2 JJs in VLSI Single Flux Quantum circuits and 0.5-mA/μm^2 JJs in high-density integrated circuits without shunt resistors.

cond-mat.supr-con↗

arXiv2016

Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating Single Flux Quantum(SFQ) digital circuits with very large scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where 'ee' denotes the process is tuned for energy efficient SFQ circuits. The former has eight superconducting layers with 0.5 μm minimum feature size and a 2 Ω/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoNx layer (Tc ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (Tc < 2 K) MoNx layer with lower nitrogen content is used for 6 Ω/sq planar resistors for shunting and biasing of Josephson junctions. Another resistive layer is added to form interlayer, sandwich-type resistors of mΩ range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlOx-Al/Nb JJs with critical current density, Jc of 100 μA/μm^2 and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The following results and topics are presented and discussed: the effect of surface topography under the JJs on the their properties and repeatability, critical current and Jc targeting, effect of hydrogen dissolved in Nb, MoNx properties for the resistor layer and for high kinetic inductance layer, technology of mΩ-range resistors.

cond-mat.supr-con↗

arXiv2014

Inductance of Circuit Structures for MIT LL Superconductor Electronics Fabrication Process with 8 Niobium Layers

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90-degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities > 10^6 Josephson junctions per cm^2 are discussed.

cond-mat.supr-con↗

arXiv2014

Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al-AlOx/Nb Josephson Junctions for VLSI Circuits

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO$_2$ interlayer dielectric. JJ electric properties and statistics such as on-chip and wafer spreads of critical current, $I_c$, normal-state conductance, $G_N$, and run-to-run reproducibility have been measured on 200-mm wafers over a broad range of JJ diameters from 200 nm to 1500 nm and critical current densities, $J_c$, from 10 kA/$cm^2$ to 50 kA/$cm^2$ where the JJs become self-shunted. Diffraction-limited photolithography of JJs is discussed. A relationship between JJ mask size, JJ size on wafer, and the minimum printable size for coherent and partially coherent illumination has been worked out. The $G_N$ and $I_c$ spreads obtained have been found to be mainly caused by variations of the JJ areas and agree with the model accounting for an enhancement of mask errors near the diffraction-limited minimum printable size of JJs. $I_c$ and $G_N$ spreads from 0.8% to 3% have been obtained for JJs with sizes from 1500 nm down to 500 nm. The spreads increase to about 8% for 200-nm JJs. Prospects for circuit densities > $10^6$ JJ/$cm^2$ and 193-nm photolithography for JJ definition are discussed.

cond-mat.supr-con↗

arXiv2012

Shadow evaporation of epitaxial Al/Al2O3/Al tunnel junctions on sapphire utilizing an inorganic bilayer mask

This letter describes a new inorganic shadow mask that has been employed for the evaporation of all-epitaxial Al/Al2O3/Al superconducting tunnel junctions. Organic resists that are commonly used for shadow masks and other lift-off processes are not compatible with ultra-high vacuum deposition systems, and they can break down at even moderately elevated temperatures. The inorganic mask described herein does not suffer these same shortcomings. It was fabricated from a Ge/Nb bilayer, comprising suspended Nb bridges supported by an undercut Ge sacrificial layer. Utilizing such a bilayer mask on C-plane sapphire, the growth of epitaxial Al tunnel junctions was achieved using molecular beam epitaxy. Crystalline Al2O3 was grown diffusively at 300 C in a molecular oxygen background of 2.0 utorr, while amorphous oxide was grown at room temperature and 25 mtorr. A variety of analysis techniques were employed to evaluate the materials, and tunnel junction current-voltage characteristics were measured at millikelvin temperatures.

cond-mat.supr-con↗

arXiv2011

Study of loss in superconducting coplanar waveguide resonators

Superconducting coplanar waveguide (SCPW) resonators have a wide range of applications due to the combination of their planar geometry and high quality factors relative to normal metals. However, their performance is sensitive to both the details of their geometry and the materials and processes that are used in their fabrication. In this paper, we study the dependence of SCPW resonator performance on materials and geometry as a function of temperature and excitation power. We measure quality factors greater than $2\times10^6$ at high excitation power and $6\times10^5$ at a power comparable to that generated by a single microwave photon circulating in the resonator. We examine the limits to the high excitation power performance of the resonators and find it to be consistent with a model of radiation loss. We further observe that while in all cases the quality factors are degraded as the temperature and power are reduced due to dielectric loss, the size of this effect is dependent on resonator materials and geometry. Finally, we demonstrate that the dielectric loss can be controlled in principle using a separate excitation near the resonance frequencies of the resonator.

cond-mat.supr-con↗