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Wilfred G. van der Wiel

Publications and source records attributed to Wilfred G. van der Wiel.

At least 19 recordsLinked to original sources

Nanoparticle Networks for Neuromorphic Computing

Physical computing leverages complex dynamical systems for energy-efficient data processing. In this work, we present a neuromorphic architecture based on metallic nanoparticles interconnected by molecular junctions on a $\text{SiO}_2$/Si substrate. We demonstrate that surrounding static control electrodes transform this nanoparticle network from a passive reservoir into a tunable nonlinear dynamical system. By analyzing how these electrodes route simple one-dimensional voltage inputs into multidimensional signal responses, we establish three core design rules to maximize computational performance. First, operating near the system's cutoff frequency achieves an optimal balance between nonlinear charge tunneling and linear capacitive memory. Second, tuning the underlying $\text{SiO}_2$ thickness sets the electrostatic screening length and dictates the memory type. Thick oxide layers reduce the screening length, causing networks larger than this length to transition into a persistent, non-volatile-like regime. Conversely, networks smaller than the screening length exhibit only fading memory. Third, introducing structural disorder via heterogeneous molecular junctions overcomes inherent limits on expressivity. While a network's computational expressivity scales with its physical size, it is ultimately capped by the screening length. Breaking internal spatial symmetries with localized disorder bypasses this saturation, allowing control voltages to independently manipulate specific signal amplitudes and phases, universally maximizing performance for dynamic neuromorphic applications.

cs.ET↗

Physical Analogue Kolmogorov-Arnold Networks based on Reconfigurable Nonlinear-Processing Units

Kolmogorov-Arnold Networks (KANs) shift neural computation from linear layers to learnable nonlinear edge functions, but implementing these nonlinearities efficiently in hardware remains an open challenge. Here we introduce a physical analogue KAN architecture in which edge functions are realized in materia using reconfigurable nonlinear-processing units (RNPUs): multi-terminal nanoscale silicon devices whose input-output characteristics are tuned via control voltages. By combining multiple RNPUs into an edge processor and assembling these blocks into a reconfigurable analogue KAN (aKAN) architecture with integrated mixed-signal interfacing, we establish a realistic system-level hardware implementation that enables compact KAN-style regression and classification with programmable nonlinear transformations. Using experimentally calibrated RNPU models and hardware measurements, we demonstrate accurate function approximation across increasing task complexity while requiring fewer or comparable trainable parameters than multilayer perceptrons (MLPs). System-level estimates indicate an energy per inference of roughly 200 pJ and an end-to-end inference latency of roughly 0.6 $μ$s for a representative workload, corresponding to over 100$\times$ reduction in energy accompanied by $>$10$\times$ reduction in area compared to a digital fixed-point MLP at similar approximation error. These results establish RNPUs as scalable, hardware-native nonlinear computing primitives and identify analogue KAN architectures as a realistic silicon-based pathway toward energy-, latency-, and footprint-efficient analogue neural-network hardware, particularly for edge inference.

cs.ET↗

Space-Charge-Driven Nonlinear Charge Transport in Silicon Reconfigurable Nonlinear-Processing Units

Reconfigurable nonlinear-processing units (RNPUs) are multi-terminal electronic devices that act as computational primitives, exploiting intrinsic nonlinear charge transport combined with electrostatic tunability. Silicon-based realizations provide a scalable and technologically relevant platform toward unconventional computing hardware, yet the physical origin of their room-temperature nonlinearity has remained unresolved. Here, we demonstrate room-temperature operation in both boron- and arsenic-doped silicon RNPUs and show, using temperature- and length-dependent measurements supported by TCAD simulations, that charge transport is governed by space-charge effects. Interface trap states strongly suppress the equilibrium carrier density, while the functional nonlinearity arises from the competition between injected carriers and ionized dopants. The resulting transport evolves from Ohmic to strongly nonlinear and space-charge-limited current regimes, as evidenced by voltage and length scaling. The opposite-polarity background doping is shown to control the onset and strength of the nonlinearity, producing behavior beyond the quadratic dependence of the classical Mott-Gurney law. Agreement between experiment and simulation supports that the spatial distribution of injected carriers and fixed charge governs the electric-field profile and device response. These results establish a space-charge-based framework for RNPUs that does not require disorder or hopping transport, and provide design guidelines for scalable, CMOS-compatible nonlinear computing hardware.

cond-mat.other↗

In-Materia Speech Recognition

With the rise of decentralized computing, as in the Internet of Things, autonomous driving, and personalized healthcare, it is increasingly important to process time-dependent signals at the edge efficiently: right at the place where the temporal data are collected, avoiding time-consuming, insecure, and costly communication with a centralized computing facility (or cloud). However, modern-day processors often cannot meet the restrained power and time budgets of edge systems because of intrinsic limitations imposed by their architecture (von Neumann bottleneck) or domain conversions (analogue-to-digital and time-to-frequency). Here, we propose an edge temporal-signal processor based on two in-materia computing systems for both feature extraction and classification, reaching a software-level accuracy of 96.2% for the TI-46-Word speech-recognition task. First, a nonlinear, room-temperature dopant-network-processing-unit (DNPU) layer realizes analogue, time-domain feature extraction from the raw audio signals, similar to the human cochlea. Second, an analogue in-memory computing (AIMC) chip, consisting of memristive crossbar arrays, implements a compact neural network trained on the extracted features for classification. With the DNPU feature extraction consuming 100s nW and AIMC-based classification having the potential for less than 10 fJ per multiply-accumulate operation, our findings offer a promising avenue for advancing the compactness, efficiency, and performance of heterogeneous smart edge processors through in-materia computing hardware.

eess.AS↗

Gradient descent in materia through homodyne gradient extraction

Deep learning, a multi-layered neural network approach inspired by the brain, has revolutionized machine learning. One of its key enablers has been backpropagation, an algorithm that computes the gradient of a loss function with respect to the weights and biases in the neural network model, in combination with its use in gradient descent. However, the implementation of deep learning in digital computers is intrinsically energy hungry, with energy consumption becoming prohibitively high for many applications. This has stimulated the development of specialized hardware, ranging from neuromorphic CMOS integrated circuits and integrated photonic tensor cores to unconventional, material-based computing system. The learning process in these material systems, realized, e.g., by artificial evolution, equilibrium propagation or surrogate modelling, is a complicated and time-consuming process. Here, we demonstrate a simple yet efficient and accurate gradient extraction method, based on the principle of homodyne detection, for performing gradient descent on a loss function directly in a physical system without the need of an analytical description. By perturbing the parameters that need to be optimized using sinusoidal waveforms with distinct frequencies, we effectively obtain the gradient information in a highly robust and scalable manner. We illustrate the method in dopant network processing units, but argue that it is applicable in a wide range of physical systems. Homodyne gradient extraction can in principle be fully implemented in materia, facilitating the development of autonomously learning material systems.

cs.NE↗

Critical nonlinear aspects of hopping transport for reconfigurable logic in disordered dopant networks

Nonlinear behavior in the hopping transport of interacting charges enables reconfigurable logic in disordered dopant network devices, where voltages applied at control electrodes tune the relation between voltages applied at input electrodes and the current measured at an output electrode. From kinetic Monte Carlo simulations we analyze the critical nonlinear aspects of variable-range hopping transport for realizing Boolean logic gates in these devices on three levels. First, we quantify the occurrence of individual gates for random choices of control voltages. We find that linearly inseparable gates such as the XOR gate are less likely to occur than linearly separable gates such as the AND gate, despite the fact that the number of different regions in the multidimensional control voltage space for which AND or XOR gates occur is comparable. Second, we use principal component analysis to characterize the distribution of the output current vectors for the (00,10,01,11) logic input combinations in terms of eigenvectors and eigenvalues of the output covariance matrix. This allows a simple and direct comparison of the behavior of different simulated devices and a comparison to experimental devices. Third, we quantify the nonlinearity in the distribution of the output current vectors necessary for realizing Boolean functionality by introducing three nonlinearity indicators. The analysis provides a physical interpretation of the effects of changing the hopping distance and temperature and is used in a comparison with data generated by a deep neural network trained on a physical device.

cs.ET↗

A kinetic Monte Carlo Approach for Boolean Logic Functionality in Gold Nanoparticle Networks

Nanoparticles interconnected by insulating organic molecules exhibit nonlinear switching behavior at low temperatures. By assembling these switches into a network and manipulating charge transport dynamics through surrounding electrodes, the network can be reconfigurably functionalized to act as any Boolean logic gate. This work introduces a kinetic Monte Carlo-based simulation tool, applying established principles of single electronics to model charge transport dynamics in nanoparticle networks. We functionalize nanoparticle networks as Boolean logic gates and assess their quality using a fitness function. Based on the definition of fitness, we derive new metrics to quantify essential nonlinear properties of the network, including negative differential resistance and nonlinear separability. These nonlinear properties are crucial not only for functionalizing the network as Boolean logic gates but also when our networks are functionalized for brain-inspired computing applications in the future. We address fundamental questions about the dependence of fitness and nonlinear properties on system size, number of surrounding electrodes, and electrode positioning. We assert the overall benefit of having more electrodes, with proximity to the network's output being pivotal for functionality and nonlinearity. Additionally, we demonstrate a optimal system size and argue for breaking symmetry in electrode positioning to favor nonlinear properties.

cs.ET↗

Toward a formal theory for computing machines made out of whatever physics offers: extended version

Approaching limitations of digital computing technologies have spurred research in neuromorphic and other unconventional approaches to computing. Here we argue that if we want to systematically engineer computing systems that are based on unconventional physical effects, we need guidance from a formal theory that is different from the symbolic-algorithmic theory of today's computer science textbooks. We propose a general strategy for developing such a theory, and within that general view, a specific approach that we call "fluent computing". In contrast to Turing, who modeled computing processes from a top-down perspective as symbolic reasoning, we adopt the scientific paradigm of physics and model physical computing systems bottom-up by formalizing what can ultimately be measured in any physical substrate. This leads to an understanding of computing as the structuring of processes, while classical models of computing systems describe the processing of structures.

cs.ET↗

Dopant Network Processing Units: Towards Efficient Neural-network Emulators with High-capacity Nanoelectronic Nodes

The rapidly growing computational demands of deep neural networks require novel hardware designs. Recently, tunable nanoelectronic devices were developed based on hopping electrons through a network of dopant atoms in silicon. These "Dopant Network Processing Units" (DNPUs) are highly energy-efficient and have potentially very high throughput. By adapting the control voltages applied to its terminals, a single DNPU can solve a variety of linearly non-separable classification problems. However, using a single device has limitations due to the implicit single-node architecture. This paper presents a promising novel approach to neural information processing by introducing DNPUs as high-capacity neurons and moving from a single to a multi-neuron framework. By implementing and testing a small multi-DNPU classifier in hardware, we show that feed-forward DNPU networks improve the performance of a single DNPU from 77% to 94% test accuracy on a binary classification task with concentric classes on a plane. Furthermore, motivated by the integration of DNPUs with memristor arrays, we study the potential of using DNPUs in combination with linear layers. We show by simulation that a single-layer MNIST classifier with only 10 DNPUs achieves over 96% test accuracy. Our results pave the road towards hardware neural-network emulators that offer atomic-scale information processing with low latency and energy consumption.

cs.LG↗

Hard superconducting gap and diffusion-induced superconductors in Ge-Si nanowires

We show a hard induced superconducting gap in a Ge-Si nanowire Josephson transistor up to in-plane magnetic fields of $250$ mT, an important step towards creating and detecting Majorana zero modes in this system. A hard induced gap requires a highly homogeneous tunneling heterointerface between the superconducting contacts and the semiconducting nanowire. This is realized by annealing devices at $180$ $^\circ$C during which aluminium inter-diffuses and replaces the germanium in a section of the nanowire. Next to Al, we find a superconductor with lower critical temperature ($T_\mathrm{C}=0.9$ K) and a higher critical field ($B_\mathrm{C}=0.9-1.2$ T). We can therefore selectively switch either superconductor to the normal state by tuning the temperature and the magnetic field and observe that the additional superconductor induces a proximity supercurrent in the semiconducting part of the nanowire even when the Al is in the normal state. In another device where the diffusion of Al rendered the nanowire completely metallic, a superconductor with a much higher critical temperature ($T_\mathrm{C}=2.9$ K) and critical field ($B_\mathrm{C}=3.4$ T) is found. The small size of diffusion-induced superconductors inside nanowires may be of special interest for applications requiring high magnetic fields in arbitrary direction.

cond-mat.mes-hall↗

Multiple Andreev reflections and Shapiro steps in a Ge-Si nanowire Josephson junction

We present a Josephson junction based on a Ge-Si core-shell nanowire with transparent superconducting Al contacts, a building block which could be of considerable interest for investigating Majorana bound states, superconducting qubits and Andreev (spin) qubits. We demonstrate the dc Josephson effect in the form of a finite supercurrent through the junction, and establish the ac Josephson effect by showing up to 23 Shapiro steps. We observe multiple Andreev reflections up to the sixth order, indicating that charges can scatter elastically many times inside our junction, and that our interfaces between superconductor and semiconductor are transparent and have low disorder.

cond-mat.mes-hall↗

New insights into the electron trapping mechanism in LaAlO_3 / SrTiO3 heterostructures

In LaAlO3/SrTiO3 heterostructures, a commonly observed but poorly understood phenomenon is that of electron trapping in back-gating experiments. In this work, by combining magnetotransport measurements and self-consistent Schroedinger-Poisson calculations, we obtain an empirical relation between the amount of trapped electrons and the gate voltage. We find that the trapped electrons follow an exponentially decaying spatial distribution away from the interface. However, contrary to earlier observations, we find that the Fermi level remains well within the quantum well. The enhanced trapping of electrons induced by the gate voltage can therefore not be explained by a thermal escape mechanism. Further gate sweeping experiments strengthen our conclusion that the thermal escape mechanism is not valid. We propose a new mechanism which involves the electromigration and clustering of oxygen vacancies in SrTiO3. Our work indicates that electron trapping is a universal phenomenon in SrTiO3-based two-dimensional electron systems.

cond-mat.mes-hall↗

Depletion-mode Quantum Dots in Intrinsic Silicon

We report the fabrication and electrical characterization of depletion-mode quantum dots in a two-dimensional hole gas (2DHG) in intrinsic silicon. We use fixed charge in a SiO$_2$/Al$_2$O$_3$ dielectric stack to induce a 2DHG at the Si/SiO$_2$ interface. Fabrication of the gate structures is accomplished with a single layer metallization process. Transport spectroscopy reveals regular Coulomb oscillations with charging energies of 10-15 meV and 3-5 meV for the few- and many-hole regimes, respectively. This depletion-mode design avoids complex multilayer architectures requiring precision alignment, and allows to adopt directly best practices already developed for depletion dots in other material systems. We also demonstrate a method to deactivate fixed charge in the SiO$_2$/Al$_2$O$_3$ dielectric stack using deep ultraviolet light, which may become an important procedure to avoid unwanted 2DHG build-up in Si MOS quantum bits.

cond-mat.mes-hall↗

A fabrication guide for planar silicon quantum dot heterostructures

We describe important considerations to create top-down fabricated planar quantum dots in silicon, often not discussed in detail in literature. The subtle interplay between intrinsic material properties, interfaces and fabrication processes plays a crucial role in the formation of electrostatically defined quantum dots. Processes such as oxidation, physical vapor deposition and atomic-layer deposition must be tailored in order to prevent unwanted side effects such as defects, disorder and dewetting. In two directly related manuscripts written in parallel we use techniques described in this work to create depletion-mode quantum dots in intrinsic silicon, and low-disorder silicon quantum dots defined with palladium gates. While we discuss three different planar gate structures, the general principles also apply to 0D and 1D systems, such as self-assembled islands and nanowires.

cond-mat.mes-hall↗

Charge transport in nanoscale vertical organic semiconductor pillar devices

We report charge transport measurements in nanoscale vertical pillar structures incorporating ultrathin layers of the organic semiconductor poly(3-hexylthiophene)(P3HT). P3HT layers with thickness down to 5 nm are gently top-contacted using wedging transfer, yielding highly reproducible, robust nanoscale junctions carrying high current densities (up to $10^6$ A/m$^2$). Current-voltage data modeling demonstrates excellent hole injection. This work opens up the pathway towards nanoscale, ultrashort-channel organic transistors for high-frequency and high-current-density operation.

cond-mat.mes-hall↗

Highly tuneable hole quantum dots in Ge-Si core-shell nanowires

We define single quantum dots of lengths varying from 60 nm up to nearly half a micron in Ge-Si core-shell nanowires. The charging energies scale inversely with the quantum dot length between 18 and 4 meV. Subsequently, we split up a long dot into a double quantum dot with a separate control over the tunnel couplings and the electrochemical potential of each dot. Both single and double quantum dot configurations prove to be very stable and show excellent control over the electrostatic environment of the dots, making this system a highly versatile platform for spin-based quantum computing.

cond-mat.mes-hall↗

Anisotropic Pauli spin blockade in hole quantum dots

We present measurements on gate-defined double quantum dots in Ge-Si core-shell nanowires, which we tune to a regime with visible shell filling in both dots. We observe a Pauli spin blockade and can assign the measured leakage current at low magnetic fields to spin-flip cotunneling, for which we measure a strong anisotropy related to an anisotropic g-factor. At higher magnetic fields we see signatures for leakage current caused by spin-orbit coupling between (1,1)-singlet and (2,0)-triplet states. Taking into account these anisotropic spin-flip mechanisms, we can choose the magnetic field direction with the longest spin lifetime for improved spin-orbit qubits.

cond-mat.mes-hall↗

Printed Circuit Board Metal Powder Filters for Low Electron Temperatures

We report the characterisation of printed circuit boards (PCB) metal powder filters and their influence on the effective electron temperature which is as low as 22 mK for a quantum dot in a silicon MOSFET structure in a dilution refrigerator. We investigate the attenuation behaviour (10 MHz- 20 GHz) of filter made of four metal powders with a grain size below 50 um. The room-temperature attenuation of a stainless steel powder filter is more than 80 dB at frequencies above 1.5 GHz. In all metal powder filters the attenuation increases with temperature. Compared to classical powder filters, the design presented here is much less laborious to fabricate and specifically the copper powder PCB-filters deliver an equal or even better performance than their classical counterparts.

cond-mat.mes-hall↗