arXiv subjects

Wilfried Steiner

Publications and source records attributed to Wilfried Steiner.

5 recordsLinked to original sources

arXiv2024

Temporal Consistency of Data and Information in Cyber-Physical Systems

In a large cyber-physical system, a temporal inconsistency of an output value can arise if there is a non-negligible delay between the instant when a sensor value is acquired from the environment and the instant when a setpoint, based on this sensor value, is used in the environment. Such a temporal inconsistency can be the cause of a critical malfunction of the cyber-physical system. This paper presents a solution of this temporal consistency problem that can best be implemented in a time-triggered architecture (TTA). In a TTA, the instants of sensor value acquisition, setpoint calculation, and actuation on the environment are statically configured, and the cyber-physical system implements software and hardware mechanisms to execute the respective actions tightly at these configured instants.

cs.NI↗

arXiv2021

Clock Synchronization in Virtualized Distributed Real-Time Systems using IEEE 802.1AS and ACRN

Virtualization of distributed real-time systems enables the consolidation of mixed-criticality functions on a shared hardware platform thus easing system integration. Time-triggered communication and computation can act as an enabler of safe hard real-time systems. A time-triggered hypervisor that activates virtual CPUs according to a global schedule can provide the means to allow for a resource efficient implementation of the time-triggered paradigm in virtualized distributed real-time systems. A prerequisite of time-triggered virtualization for hard real-time systems is providing access to a global time base to VMs as well as to the hypervisor. A global time base is the result of clock synchronization with an upper bound on the clock synchronization precision. We present a formalization of the notion of time in virtualized real-time systems. We use this formalization to propose a virtual clock condition that enables us to test the suitability of a virtual clock for the design of virtualized time-triggered real-time systems. We discuss and model how virtualization, in particular resource consolidation versus resource partitioning, degrades clock synchronization precision. Finally, we apply our insights to model the IEEE~802.1AS clock synchronization protocol and derive an upper bound on the clock synchronization precision of IEEE 802.1AS. We present our implementation of a dependent clock for ACRN that can be synchronized to a grandmaster clock. The results of our experiments illustrate that a type-1 hypervisor implementing a dependent clock yields native clock synchronization precision. Furthermore, we show that the upper bound derived from our model holds for a series of experiments featuring native as well as virtualized setups.

cs.DC↗

arXiv2020

The FORA Fog Computing Platform for Industrial IoT

Industry 4.0 will only become a reality through the convergence of Operational and Information Technologies (OT & IT), which use different computation and communication technologies. Cloud Computing cannot be used for OT involving industrial applications, since it cannot guar-antee stringent non-functional requirements, e.g., dependability, trustworthiness and timeliness. Instead, a new computing paradigm, called Fog Computing, is envisioned as an architectural means to realize the IT/OT convergence. In this paper we propose a Fog Computing Platform (FCP) reference architecture targeting Industrial IoT applications. The FCP is based on: deter-ministic virtualization that reduces the effort required for safety and security assurance; middle-ware for supporting both critical control and dynamic Fog applications; deterministic networking and interoperability, using open standards such as IEEE 802.1 Time-Sensitive Networking (TSN) and OPC Unified Architecture (OPC UA); mechanisms for resource management and or-chestration; and services for security, fault tolerance and distributed machine learning. We pro-pose a methodology for the definition and the evaluation of the reference architecture. We use the Architecture Analysis Design Language (AADL) to model the FCP reference architecture, and a set of industrial use cases to evaluate its suitability for the Industrial IoT area.

cs.DC↗

arXiv2017

Formal Scheduling Constraints for Time-Sensitive Networks

In recent years, the IEEE 802.1 Time Sensitive Networking (TSN) task group has been active standardizing time-sensitive capabilities for Ethernet networks ranging from distributed clock synchronization and time-based ingress policing to frame preemption, redundancy management, and scheduled traffic enhancements. In particular the scheduled traffic enhancements defined in IEEE 802.1Qbv together with the clock synchronization protocol open up the possibility to schedule communication in distributed networks providing real-time guarantees. In this paper we formalize the necessary constraints for creating window-based IEEE~802.1Qbv Gate Control List schedules for Time-sensitive Networks (TSN). The resulting schedules allow a greater flexibility in terms of timing properties while still guaranteeing deterministic communication with bounded jitter and end-to-end latency.

cs.NI↗

arXiv2016

ARSENAL: Automatic Requirements Specification Extraction from Natural Language

Requirements are informal and semi-formal descriptions of the expected behavior of a complex system from the viewpoints of its stakeholders (customers, users, operators, designers, and engineers). However, for the purpose of design, testing, and verification for critical systems, we can transform requirements into formal models that can be analyzed automatically. ARSENAL is a framework and methodology for systematically transforming natural language (NL) requirements into analyzable formal models and logic specifications. These models can be analyzed for consistency and implementability. The ARSENAL methodology is specialized to individual domains, but the approach is general enough to be adapted to new domains.

cs.CL↗