Xiaomei Tang | Searcharxiv

arXiv2026

A Low-Complexity Joint Fractional Delay and Doppler Frequency Estimator for AFDM-Enabled Vehicular LEO-ICAN Systems

Low-Earth-orbit (LEO) satellites and vehicle-to-everything (V2X) networks are driving integrated communication and navigation (ICAN) toward next-generation intelligent transportation. Affine frequency division multiplexing (AFDM) is a promising waveform for high-mobility LEO scenarios owing to its Doppler robustness, simple modulation, and low pilot overhead. However, applying existing high-accuracy AFDM fractional delay-Doppler estimators to LEO-ICAN entails substantial search or inference complexity, while the spectrum-wrapping-induced envelope structure in line-of-sight (LOS)-dominated channels remains underexploited. This paper analyzes and exploits the spectrum-wrapping-induced envelope structure of the fractional AFDM response, and proposes a low-complexity joint estimator that combines minimum-entropy fractional Doppler estimation with closed-form fractional delay estimation. Simulation results show that the proposed estimator approaches the root Cramér--Rao lower bound (RCRLB) and achieves root-mean-square error (RMSE) performance comparable to that of matched filtering (MF), matched filtering with generalized Fibonacci search (MF-GFS), and off-grid sparse Bayesian learning (OG-SBL), while requiring substantially lower computational complexity and runtime. This favorable accuracy-complexity profile highlights the potential of the proposed estimator for real-time ICAN processing in high-mobility LEO-assisted vehicular networks.

eess.SP↗

arXiv2025

Cost-Effective Optimization and Implementation of the CRT-Paillier Decryption Algorithm for Enhanced Performance

To address the privacy protection problem in cloud computing, privacy enhancement techniques such as the Paillier additive homomorphism algorithm are receiving widespread attention. Paillier algorithm allows addition and scalar multiplication operations in dencrypted state, which can effectively protect privacy. However, its computational efficiency is limited by complex modulo operations due to the ciphertext expansion followed by encryption. To accelerate its decryption operation, the Chinese Remainder Theorem (CRT) is often used to optimize these modulo operations, which lengthens the decryption computation chain in turn. To address this issue, we propose an eCRT-Paillier decryption algorithm that shortens the decryption computation chain by combining precomputed parameters and eliminating extra judgment operations introduced by Montgomery modular multiplications. These two improvements reduce 50% modular multiplications and 60% judgment operations in the postprocessing of the CRT-Paillier decryption algorithm. Based on these improvements, we propose a highly parallel full-pipeline architecture to eliminate stalls caused by multiplier reuse in traditional modular exponentiation operations. This architecture also adopts some optimizations such as simplifying modular exponentiation units by dividing the exponent into segments and parallelizing data flow by multi-core instantiation. Finally, a high-throughput and efficient Paillier accelerator named MESA was implemented on the Xilinx Virtex-7 FPGA for evaluation, which can complete a decryption using 2048-bit key within 0.577ms under 100 MHz clock frequency. Compared to prior works, MESA demonstrates a throughput improvement of 1.16 to 313.21 under identical conditions, also with enhancements in area efficiency for LUT, DSP, and FF of 3.32 to 117.55, 1.49 to 1.64, and 2.94 to 9.94, respectively.

cs.CR↗