Xuchao Xie | Searcharxiv

arXiv2026

NeuroPDE+: A Scalable Neuromorphic PDE Accelerator Based on Spintronic and Ferroelectric Devices

The pursuit of high-performance PDE solvers rests on three fundamental challenges: (i) the curse of dimensionality in kinetic and financial equations, (ii) the poor extrapolation of purely data-driven surrogates, and (iii) the widening gap between algorithm design and hardware specialization. To overcome these challenges, we present NeuroPDE+, a scalable neuromorphic PDE solver design based on spintronic and ferroelectric devices for accelerating PDE solutions. NeuroPDE+ consists of two dedicated units: a diffusion tracking unit (DTU), which emulates random walks on Markov chains through activations between hardware neurons, and a scattering tracking unit (STU), which samples non-local jumps via a multi-level probability tree. System-level simulations suggest that NeuroPDE+ achieves a squared error below 1e-2 in steady-state heat equation and particle transport problems. Simulation results further indicate that the DTU achieves up to a 315x performance gain over previous neuromorphic processors, and that the STU achieves a 1000x speedup compared to a general-purpose CPU. Co-designing algorithm and hardware with intrinsic stochasticity and non-volatile in-memory computing, NeuroPDE+ preliminarily explores a new paradigm for efficient and scalable neuromorphic PDE solvers. This approach could pave the way for probabilistic computing architectures in large-scale scientific simulations.

cs.AR↗

arXiv2026

C2P-Cache: Scalable GPU L1 Cache Sharing via Concurrent Candidate Pruning

Modern GPUs rely on private per-SM L1 caches and a shared L2 cache, but this organization obscures cross-SM reuse: an L1 miss is typically forwarded to L2 even when the requested line already resides in a peer L1 cache, leading to redundant L2 access. Prior GPU L1-sharing designs attempt to recover such reuse through exact or broad remote-hit searches, which become increasingly difficult to scale and can interfere with the critical L1 miss path under high concurrency. %miss handling as more caches participate and more misses arrive concurrently. We observe that eliminating redundant L2 accesses does not require exact, chip-wide knowledge of private L1 contents. Instead, it requires only sufficient visibility to sharply narrow down a small set of candidate caches, leaving exact confirmation to a much smaller number of L1s. Based on this insight, we propose C2P-Cache, a scalable GPU L1-sharing mechanism that transforms remote-hit discovery from a chip-wide exact search problem into a lightweight filtering-and-confirmation process. C2P-Cache maintains compact Bloom-filter-based snapshots of private L1 tags, performs parallel chip-wide candidate filtering, and selectively probes only a small number of likely peer caches. To sustain high concurrency, C2P-Cache organizes filtering as bit-sliced matching over a banked and replicated snapshot matrix, enabling efficient, parallel processing of many concurrent misses without interfering with normal L1 accesses. Across a wide range of GPU workloads, C2P-Cache improves instructions per cycle (IPC) by up to 49.7\% and by 23.5\% on average for applications with high remote-L1 reuse and strong sensitivity to L2 latency, demonstrating that lightweight, scalable filtering can effectively unlock cross-SM reuse with modest overhead.

cs.AR↗