arXiv subjects

Yao-Jen Lee

Publications and source records attributed to Yao-Jen Lee.

6 recordsLinked to original sources

arXiv2022

Alleviation of Temperature Variation Induced Accuracy Degradation in Ferroelectric FinFET Based Neural Network

This paper reports the impacts of temperature variation on the inference accuracy of pre-trained all-ferroelectric FinFET deep neural networks, along with plausible design techniques to abate these impacts. We adopted a pre-trained artificial neural network (N.N.) with 96.4% inference accuracy on the MNIST dataset as the baseline. As an aftermath of temperature change, a compact model captured the conductance drift of a programmed cell over a wide range of gate biases. We observed a significant inference accuracy degradation in the analog neural network at 233 K for an N.N. trained at 300 K. Finally, we deployed binary neural networks with "read voltage" optimization to ensure immunity of N.N. to accuracy degradation under temperature variation, maintaining an inference accuracy of 96%. Keywords: Ferroelectric memories

cs.LG↗

arXiv2022

Neuromorphic Computing with Ferroelectric FinFETs in the Presence of Temperature, Process Variation, Device Aging and Flicker Noise

This paper reports a comprehensive study on the impacts of temperature-change, process variation, flicker noise and device aging on the inference accuracy of pre-trained all-ferroelectric (FE) FinFET deep neural networks. Multiple-level-cell (MLC) operation with a novel adaptive-program-and-read algorithm with 100ns write pulse has been experimentally demonstrated in 5 nm thick hafnium zirconium oxide (HZO)-based FE-FinFET. With pre-trained neural network (NN) with 97.5% inference accuracy on MNIST dataset as baseline, device to device variation is shown to have negligible impact. Flicker noise characterization at various bias conditions depicts that drain current fluctuation is less than 0.7% with virtually no inference accuracy degradation. The conductance drift of a programmed cell, as an aftermath of temperature change, was captured by a compact model over a wide range of gate biases. Despite significant inference accuracy degradation at 233K for a NN trained at 300K, gate bias optimization for recovering the accuracy is demonstrated. Endurance above 10$^8$ cycles and extrapolated retention above 10 years are shown, which paves the way for edge device artificial intelligence with FE-FinFETs.

cs.ET↗

arXiv2021

Analytical Modelling of Ferroelectricity Instigated Enhanced Electrostatic Control in Short-Channel FinFETs

This study simulated negative-capacitance double gate FinFETs with channel lengths ranging from 25nm to 100nm using TCAD. The results show that negative capacitance significantly reduces subthreshold swing as well as drain induced barrier lowering effects. The improvement is found to be significantly more prominent for short channel devices than long ones, which demonstrates the tremendous advantage of negative capacitance gate stack for scaled MOSFETs. A compact analytical formulation is developed to quantify sub-threshold swing improvement for short channel devices.

physics.app-ph↗

arXiv2020

Formation of Uniform Crystal and Reduction of Electrical Variation in HfZrO$_2$ Ferroelectric Memory by Thermal Engineering

In this paper we proclaim excellent variation control in Hf$_{0.5}$Zr$_{0.5}$O$_2$ based ferroelectric films obtained by germination of large ferroelectric domain via extended duration of thermal annealing. 10nm thick Hf$_{0.5}$Zr$_{0.5}$O$_2$ based ferroelectric capacitors with TiN as bottom and top electrodes are fabricated and characterized. The duration of rapid thermal annealing (RTA) is varied to observe its effect on crystal formation and device electrical properties at 700C. The device to device variation in terms of coercive voltage and peak capacitance are reduced from 0.4V to 0.01V and from 2*$10^{-5}$nF/cm$^2$ to 4*$10^{-6}$nF/cm$^2$, respectively, by increasing the RTA duration. High resolution transmission electron micrograph clearly shows large and uniform ferroelectric domains with RTA of 180 seconds. Extended duration of RTA likely allows uniform crystal to form, which mitigates the stochasticity of the distribution of ferroelectric and paraelectric domains, and deterministic switching has been infused. This improvement paves the way for implementing Hf$_{0.5}$Zr$_{0.5}$O$_2$ based deeply scaled devices for memory and steep slope device applications.

physics.app-ph↗

arXiv2020

A computationally efficient compact model for ferroelectric FETs for the simulation of online training of neural networks

Tri-gate ferroelectric FETs with Hf0.5Zr0.5O2 gate insulator for memory and neuromorphic applications are fabricated and characterized for multi-level operation. The conductance and threshold voltage exhibit highly linear and symmetric characteristics. A compact analytical model is developed to accurately capture FET transfer characteristics, including series resistance, coulombic scattering, and vertical field dependent mobility degradation effects, as well as the evolvement of threshold voltage and mobility with ferroelectric polarization switching. The model covers both sub-threshold and strong inversion operation. Additional measurements confirm ferroelectric switching as opposed to carrier-trapping-based memory operation. The compact model is implemented in a simulation platform for online training of deep neural networks.

physics.app-ph↗

arXiv2017

Large-Area Two-Dimensional Layered MoTe$_2$ by Physical Vapor Deposition and Solid-Phase Crystallization in a Tellurium-Free Atmosphere

Molybdenum ditelluride (MoTe$_2$) has attracted considerable interest for nanoelectronic, optoelectronic, spintronic, and valleytronic applications because of its modest band gap, high field-effect mobility, large spin-orbit-coupling splitting, and tunable 1T'/2H phases. However, synthesizing large-area, high-quality MoTe$_2$ remains challenging. The complicated design of gas-phase reactant transport and reaction for chemical vapor deposition or tellurization is nontrivial because of the weak bonding energy between Mo and Te. Here, we report a new method for depositing MoTe$_2$ that entails using physical vapor deposition followed by a post-annealing process in a Te-free atmosphere. Both Mo and Te were physically deposited onto the substrate by sputtering a MoTe$_2$ target. A composite SiO$_2$ capping layer was designed to prevent Te sublimation during the post-annealing process. The post-annealing process facilitated 1T'-to-2H phase transition and solid-phase crystallization, leading to the formation of high-crystallinity few-layer 2H-MoTe$_2$ with a field-effect mobility of ~10 cm$^2$/(V-s), the highest among all nonexfoliated 2H-MoTe$_2$ currently reported. Furthermore, 2H-MoS$_2$ and Td-WTe$_2$ can be deposited using similar methods. Requiring no transfer or chemical reaction of metal and chalcogen reactants in the gas phase, the proposed method is potentially a general yet simple approach for depositing a wide variety of large-area, high-quality, two-dimensional layered structures.

cond-mat.mtrl-sci↗