arXiv subjects

Yerzhan Mustafa

Publications and source records attributed to Yerzhan Mustafa.

4 recordsLinked to original sources

arXiv2026

Reed-Muller Error-Correction Code Encoder for SFQ-to-CMOS Interface Circuits

Data transmission from superconducting digital electronics such as single flux quantum (SFQ) logic to semiconductor (CMOS) circuits is subject to bit errors due to, e.g., flux trapping, process parameter variations (PPV), and fabrication defects. In this paper, a lightweight hardware-efficient error-correction code encoder is designed and analyzed. Particularly, a Reed-Muller code RM(1,3) encoder is implemented with SFQ digital logic. The proposed RM(1,3) encoder converts a 4-bit message into an 8-bit codeword and can detect and correct up to 3- and 1-bit errors, respectively. This encoder circuit is designed using MIT-LL SFQ5ee process and SuperTools/ColdFlux RSFQ cell library. A simulation framework integrating JoSIM simulator and MATLAB script for automated data collection and analysis, is proposed to study the performance of RM(1,3) encoder. The proposed encoder improves the probability of having no bit errors by 6.7% as compared to an encoder-less design under $\pm20\%$ PPV. With $\pm15\%$ and lower PPV, the proposed encoder could correct all errors with at least 99.1% probability. The impact of fabrication defects such as open circuit faults on the encoder circuit is also studied using the proposed framework.

eess.SP↗

arXiv2026

Interfacing Superconductor and Semiconductor Digital Electronics

Interface circuits are the key components that enable the hybrid integration of superconductor and semiconductor digital electronics. The design requirements of superconductor-semiconductor interface circuits vary depending on the application, such as high-performance classical computing, superconducting quantum computing, and digital signal processing. In this survey, various interface circuits are categorized based on the working principle and structure. The superconducting output drivers are explored, which are capable of converting and amplifying, e.g., single flux quantum (SFQ) voltage pulses, to voltage levels that semiconductor circuits can process. Several trade-offs between circuit- and system-level design parameters are examined. Accordingly, parameters such as the data rate, output voltage, power dissipation, layout area, thermal/heat load of cryogenic cables, and bit-error rate are considered.

physics.app-ph↗

arXiv2025

Lightweight Error-Correction Code Encoders in Superconducting Electronic Systems

Data transmission from superconducting electronic circuits, such as single flux quantum (SFQ) logic, to room-temperature electronics is susceptible to bit errors, which may result from flux trapping, fabrication defects, and process parameter variations (PPV). Due to the cooling power budget at 4.2 K and constraints on the chip area, the size of the error-correction code encoders is limited. In this work, three lightweight error-correction code encoders are proposed that are based on Hamming(7,4), Hamming(8,4), and Reed-Muller(1,3) codes and implemented with SFQ logic. The performance of these encoders is analyzed in the presence of PPV. The trade-offs between the theoretical complexity and physical size of error-correction code encoders are identified.

eess.SP↗

arXiv2021

Modeling and Analysis of Switched-Capacitor Converters as a Multi-port Network for Covert Communication

Switched-capacitor (SC) DC-DC voltage converters are widely used in power delivery and management of modern integrated circuits. Connected to a common supply voltage, SC converters exhibit cross-regulation/coupling effects among loads connected to different SC converter stages due to the shared components such as switches, capacitors, and parasitic elements. The coupling effects between SC converter stages can potentially be used in covert communication, where two or more entities (e.g., loads) illegitimately establish a communication channel to exchange malicious information stealthily. To qualitatively analyze the coupling effects, a novel modeling technique is proposed based on the multi-port network theory. The fast and slow switching limit (FSL and SSL) equivalent resistance concepts are used to analytically determine the impact of each design parameter such as switch resistance, flying capacitance, switching frequency, and parasitic resistance. A three-stage 2:1 SC converter supplying three different loads is considered as a case study to verify the proposed modeling technique.

eess.SY↗