arXiv subjects

Yida Li

Publications and source records attributed to Yida Li.

9 recordsLinked to original sources

arXiv2026

VeRA+: Vector-Based Lightweight Digital Compensation for Drift-Resilient RRAM In-Memory Computing

RRAM-based in-memory computing (IMC) offers high energy efficiency but suffers from conductance drift that severely degrades long-term accuracy. Existing approaches including retraining, noise-aware training, and Batch Normalization (BN)-based calibration either require RRAM rewriting, demand large storage overhead, or rely on online correction. We propose VeRA+, a lightweight drift compensation framework that reuses shared projection matrices and introduces only two compact drift-specific vectors per drift level. A drift-aware scheduling algorithm offline-trains a small set of VeRA+ parameters and selects the appropriate set over time without any on-chip retraining or data replay. VeRA+ preserves up to 99.77% of the drift-free accuracy after ten years of simulated drift and reduces storage overhead by more than three orders of magnitude compared with BN-based calibration. To validate VeRA+ under realistic device behavior, we extract one-week drift statistics from measurements on our fabricated 1T1R RRAM devices and use them to simulate realistic drifted weights. Under these measured drift conditions, VeRA+ achieves accuracy close to the drift-free baseline, providing an efficient and practical solution for long-term drift resilience in RRAM-IMC.

cs.AR↗

arXiv2024

CIER: A Novel Experience Replay Approach with Causal Inference in Deep Reinforcement Learning

In the training process of Deep Reinforcement Learning (DRL), agents require repetitive interactions with the environment. With an increase in training volume and model complexity, it is still a challenging problem to enhance data utilization and explainability of DRL training. This paper addresses these challenges by focusing on the temporal correlations within the time dimension of time series. We propose a novel approach to segment multivariate time series into meaningful subsequences and represent the time series based on these subsequences. Furthermore, the subsequences are employed for causal inference to identify fundamental causal factors that significantly impact training outcomes. We design a module to provide feedback on the causality during DRL training. Several experiments demonstrate the feasibility of our approach in common environments, confirming its ability to enhance the effectiveness of DRL training and impart a certain level of explainability to the training process. Additionally, we extended our approach with priority experience replay algorithm, and experimental results demonstrate the continued effectiveness of our approach.

cs.LG↗

arXiv2023

Non-Hermitian effect to the ballistic transport and quantized Hall conductivity in 2H-MoS$_{2}$

By designing a multi-channel millimeter Hall measurement configuration, we realize the carrier-density (locally) controllable measurement on the transport property in 2H MoS$_{2}$. We observe a linearly increased Hall conductivity and exponentially decreased resistivity as the increase of dc current. The intrinsically large band gap does not exhibit too much effect on our measurement, as far as the magnetic field is above the critical value, which is $B=6$ T for 2H-MoS$_{2}$. Instead, the edge effect which emerge as a result of one-dimensional channels. This is different from the Corbino geometry which is widely applied on semiconductors, where the edges are absent. At room temperature, we observe that the emergent quantized quantum Hall plateaus are at the same value for both the two measurements, which implies that the quantized conductivity does not depends on the non-Hermitian interactions, but the number of partially filled Landau levels, and this is in consistent with the previous theoretical works\cite{Siddiki}. At low-temperature limit, the Hall plateaus are destroyed due to the filtered contribution from the electrons above fermi energy, and in this case, the two measuremens exhibits stronger distinction, where we observe stronger fluctuations (of voltage, conductivity, and resistivity) at the currents between where there are Hall plateaus at higher temperature.

cond-mat.mes-hall↗

arXiv2023

Sub-5-nm Ultra-thin In$_2$O$_3$ Transistors for High-Performance and Low-Power Electronic Applications

Ultra-thin (UT) oxide semiconductors are promising candidates for back-end-of-line (BEOL) compatible transistors and monolithic three-dimensional integration. Experimentally, UT indium oxide (In$_2$O$_3$) field-effect transistors (FETs) with thicknesses down to 0.4 nm exhibits extremely high drain current (10000 $\mu$A/$\mu$m) and transconductance (4000 $\mu$S/$\mu$m). Here, we employ the ab initio quantum transport simulation to investigate the performance limit of sub-5-nm gate length (Lg) UT In$_2$O$_3$ FET. Based on the International Technology Roadmap for Semiconductors (ITRS) criteria for high-performance (HP) devices, the scaling limit of UT In$_2$O$_3$ FETs can reach 2 nm in terms of on-state current, delay time, and power dissipation. The wide bandgap nature of UT In$_2$O$_3$ (3.15 eV) renders it a suitable candidate for ITRS low-power (LP) electronics with Lg down to 3 nm. Both the HP and LP UT In$_2$O$_3$ FETs exhibit superior energy-delay products as compared to other common 2D semiconductors such as monolayer MoS2 and MoTe2. Our study unveils the immense promise of UT In$_2$O$_3$ for both HP and LP device applications.

physics.app-ph↗

arXiv2023

Realizing In-Memory Baseband Processing for Ultra-Fast and Energy-Efficient 6G

To support emerging applications ranging from holographic communications to extended reality, next-generation mobile wireless communication systems require ultra-fast and energy-efficient baseband processors. Traditional complementary metal-oxide-semiconductor (CMOS)-based baseband processors face two challenges in transistor scaling and the von Neumann bottleneck. To address these challenges, in-memory computing-based baseband processors using resistive random-access memory (RRAM) present an attractive solution. In this paper, we propose and demonstrate RRAM-implemented in-memory baseband processing for the widely adopted multiple-input-multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) air interface. Its key feature is to execute the key operations, including discrete Fourier transform (DFT) and MIMO detection using linear minimum mean square error (L-MMSE) and zero forcing (ZF), in one-step. In addition, RRAM-based channel estimation module is proposed and discussed. By prototyping and simulations, we demonstrate the feasibility of RRAM-based full-fledged communication system in hardware, and reveal it can outperform state-of-the-art baseband processors with a gain of 91.2$\times$ in latency and 671$\times$ in energy efficiency by large-scale simulations. Our results pave a potential pathway for RRAM-based in-memory computing to be implemented in the era of the sixth generation (6G) mobile communications.

eess.SP↗

arXiv2022

Realizing Ultra-Fast and Energy-Efficient Baseband Processing Using Analogue Resistive Switching Memory

To support emerging applications ranging from holographic communications to extended reality, next-generation mobile wireless communication systems require ultra-fast and energy-efficient (UFEE) baseband processors. Traditional complementary metal-oxide-semiconductor (CMOS)-based baseband processors face two challenges in transistor scaling and the von Neumann bottleneck. To address these challenges, in-memory computing-based baseband processors using resistive random-access memory (RRAM) present an attractive solution. In this paper, we propose and demonstrate RRAM-based in-memory baseband processing for the widely adopted multiple-input-multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) air interface. Its key feature is to execute the key operations, including discrete Fourier transform (DFT) and MIMO detection using linear minimum mean square error (L-MMSE) and zero forcing (ZF), in one-step. In addition, RRAM-based channel estimation as well as mapper/demapper modules are proposed. By prototyping and simulations, we demonstrate that the RRAM-based full-fledged communication system can significantly outperform its CMOS-based counterpart in terms of speed and energy efficiency by $10^3$ and $10^6$ times, respectively. The results pave a potential pathway for RRAM-based in-memory computing to be implemented in the era of the sixth generation (6G) mobile communications.

eess.SP↗

arXiv2015

Tuning the Threshold Voltage of MoS2 Field-Effect Transistors via Surface Treatment

Controlling the threshold voltage (Vth) of a field-effect transistor is important for realizing robust logic circuits. Here, we report a facile approach to achieve bidirectional Vth tuning of molybdenum disulfide (MoS2) field-effect transistors. By increasing and decreasing the amount of sulfur vacancies in the MoS2 surface, the Vth of MoS2 transistors can be left- and right-shifted, respectively. Transistors fabricated on perfect MoS2 flakes are found to exhibit two-fold enhancement in mobility and a very positive Vth. More importantly, our elegant hydrogen treatment is able to tune the large Vth to a small value without any performance degradation simply by reducing the atomic ratio of S:Mo slightly; in other words, creating a certain amount of sulfur vacancies in the MoS2 surface, which generate defect states in the band gap of MoS2 that mediate conduction of a MoS2 transistor in the subthreshold regime. First-principles calculations further indicate that the edge and width of defect band can be tuned according to the vacancy density. This work not only demonstrates for the first time the ease in tuning the Vth of MoS2 transistors, but also offers a process technology solution that is critical for further development of MoS2 as a mainstream electronic material.

cond-mat.mes-hall↗

arXiv2014

Low Resistance Metal Contacts to MoS2 Devices with Nickel-Etched-Graphene Electrodes

We report an approach to achieve low-resistance contacts to MoS2 transistors with the intrinsic performance of the MoS2 channel preserved. Through a dry transfer technique and a metal-catalyzed graphene treatment process, nickel-etched-graphene electrodes were fabricated on MoS2 that yield contact resistance as low as 200 ohm-um. The substantial contact enhancement (~2 orders of magnitude) as compared to pure nickel electrodes, is attributed to the much smaller work function of nickel-graphene electrodes, together with the fact that presence of zigzag edges in the treated graphene surface enhances tunneling between nickel and graphene. To this end, the successful fabrication of a clean graphene-MoS2 interface and a low resistance nickel-graphene interface is critical for the experimentally measured low contact resistance. The potential of using graphene as an electrode interlayer demonstrated in this work paves the way towards achieving high performance next-generation transistors.

cond-mat.mes-hall↗

arXiv2014

Gold on WSe2 Single Crystal Film as a Substrate for Surface Enhanced Raman Scattering (SERS) Sensing

Synthesis and characterization of high-quality single-crystal WSe2 films on highly-insulating substrate is presented. We demonstrate for the first time that the presence of gold nanoparticles in the basal plane of a WSe2 film can enhance its Raman scattering intensity. The experimentally observed enhancement ratio in the Raman signal correlates well with the simulated electric field intensity using a three-dimensional electromagnetic software and theoretical calculation. This work provides guidelines for the use of two-dimensional WSe2 films as a SERS substrate.

cond-mat.mes-hall↗