arXiv subjects

Yimin Gao

Publications and source records attributed to Yimin Gao.

7 recordsLinked to original sources

arXiv2026

FlexPosit: Tunable Fractional Precision for LLM Inference Accelerators

Large language models (LLMs) offer remarkable capabilities but impose prohibitive compute and energy costs. Quantization governs the trade-offs between accuracy and hardware efficiency across granularity and bit-width. Finer granularity (e.g., group-wise) provides high accuracy but incurs scaling and control overhead, while coarser granularity (e.g., channel-wise) has lower overhead but loses accuracy at low precision. Meanwhile, mixed-precision quantization exposes rich accuracy-efficiency trade-offs algorithmically, but existing LLM accelerators remain limited to discrete precision modes, leaving the fractional design space between them unexplored. FlexPosit bridges these gaps through co-design of Posit-based quantization and a precision-tunable bit-serial architecture. Algorithmically, FlexPosit employs distribution-aware quantization with hardware-aligned, sensitivity-guided mixed-precision allocation, leveraging the Posit format's tapered precision to achieve group-wise-like accuracy with channel-wise-like regularity. Architecturally, FlexPosit is a unified bit-serial systolic array with lightweight per-column decoders, unified Processing Elements (PEs), and a global precision controller, enabling tunable fractional precision while preserving fully regular systolic dataflow. Across diverse LLMs, FlexPosit achieves near-FP16 accuracy with sub-5-bit fractional weights. It achieves 1.8x higher throughput and 1.2x lower energy than BitMoD (group-wise quantization), and 1.5x higher throughput and 2.0x lower energy than OliVe (channel-wise quantization), establishing a new Pareto frontier for precision-tunable LLM acceleration.

cs.AR↗

arXiv2026

Modeling and Resource Optimization for Quantum Oracles

Quantum oracles are fundamental building blocks of many quantum algorithms, and their resource consumption directly affects performance, yet structured description and complexity analysis for their composition are still lacking. In this paper, we introduce the Framework for Oracle Recursion Modeling (FORM), a unified formal abstraction of multi-function composition in quantum oracles: it provides a structured description of the composition layer, makes its gate complexity exactly computable, and turns oracle design into an optimizable tree-construction problem. Based on this model, we propose the ShallowGrow algorithm, which constructs an oracle structure under a given ancilla budget and provably minimizes the number of function evaluations. On Boolean quadratic equation systems, ShallowGrow reduces Qiskit-measured circuit depth by 54.1% on average relative to the state-of-the-art W-cycle construction, with consistent reductions on the EPFL and ISCAS85 combinational logic networks under scarce ancilla budgets. Furthermore, pebbling-based syntheses trade space against time within the logic network of a function; ShallowGrow extends this trade-off across functions, and integrated with their published circuits it reduces the ancillary qubits of a complete oracle from one per constraint function to logarithmically many. With half as many ancillas as constraint functions, the T-count falls by a factor of 7.9 to 32 relative to the W-cycle-based construction.

quant-ph↗

arXiv2026

High-Performance Low-Power Adiabatic Systolic Array Design in Advanced FinFET Nodes

Adiabatic logic has traditionally been recognized as a low-power solution but constrained to low clock speeds to preserve adiabatic behavior. For advanced FinFET nodes, however, clock frequencies have plateaued due to power/thermal concerns (dark silicon) even as the intrinsic device speeds have continued to scale. This convergence opens an opportunity for adiabatic logic to maintain adiabatic behavior even at GHz clocks. We demonstrate an adiabatic logic (AL) design methodology through a MAC systolic array implemented in commercial 16 nm FinFET technology with a resonant 4-phase power clock (PCK) generator, including digital-to-AL and AL-to-digital interfaces. Simulations show that the AL MAC systolic array at 1 GHz achieves power reductions of up to 42% and 36% at the core and system levels, respectively, compared to digital counterparts. Scaling to more advanced nodes should provide even better power/performance metrics.

cs.AR↗

arXiv2026

Guarded Equivalence Predicates for Scalable Formal Hardware Information-Flow Verification

Formal hardware information-flow verification is a principled way to rule out secret-dependent functional or timing observations, but scaling such proofs remains difficult. Self-composition reduces information-flow verification to safety checking over two circuit copies, creating relational proof obligations that are hard for a generic PDR engine to discover from bit-level logic alone. Recent PDR-based techniques exploit this duplicated structure through copy symmetry and global cross-copy equivalence predicates. These predicates are effective when corresponding internal signals agree throughout the reachable state space, but they do not capture equalities that are relevant only in a specific control context. We observe that such contextual relations arise naturally in hardware IFV proofs: an internal signal pair may need to agree only within a control phase, transaction window, loop state, or protocol region. We introduce guarded equivalence predicates to expose these relations to PDR. Rather than treating a proposed contextual equality as an assumption, the verifier submits the corresponding mismatch condition as an auxiliary blocking obligation. Guards are proposed from relational counterexamples-to-induction using CTI-local extraction and state-split search; only candidates proved unreachable by the backend affect the proof. Across 12 IFV benchmarks and two PDR backends, guarded predicates convert two contextual baseline timeouts into completed proofs within 34.2--89.5s under an 1800s limit, while reducing proof time by up to 10.8x on additional benchmarks.

cs.CR↗

arXiv2025

EDA-Q: Electronic Design Automation for Superconducting Quantum Chip

Electronic Design Automation (EDA) plays a crucial role in classical chip design and significantly influences the development of quantum chip design. However, traditional EDA tools cannot be directly applied to quantum chip design due to vast differences compared to the classical realm. Several EDA products tailored for quantum chip design currently exist, yet they only cover partial stages of the quantum chip design process instead of offering a fully comprehensive solution. Additionally, they often encounter issues such as limited automation, steep learning curves, challenges in integrating with actual fabrication processes, and difficulties in expanding functionality. To address these issues, we developed a full-stack EDA tool specifically for quantum chip design, called EDA-Q. The design workflow incorporates functionalities present in existing quantum EDA tools while supplementing critical design stages such as device mapping and fabrication process mapping, which users expect. EDA-Q utilizes a unique architecture to achieve exceptional scalability and flexibility. The integrated design mode guarantees algorithm compatibility with different chip components, while employing a specialized interactive processing mode to offer users a straightforward and adaptable command interface. Application examples demonstrate that EDA-Q significantly reduces chip design cycles, enhances automation levels, and decreases the time required for manual intervention. Multiple rounds of testing on the designed chip have validated the effectiveness of EDA-Q in practical applications.

cs.ET↗

arXiv2025

Membrane: Accelerating Database Analytics with Bank-Level DRAM-PIM Filtering

In-memory database query processing frequently involves substantial data transfers between the CPU and memory, leading to inefficiencies due to Von Neumann bottleneck. Processing-in-Memory (PIM) architectures offer a viable solution to alleviate this bottleneck. In our study, we employ a commonly used software approach that streamlines JOIN operations into simpler selection or filtering tasks using pre-join denormalization which makes query processing workload more amenable to PIM acceleration. This research explores DRAM design landscape to evaluate how effectively these filtering tasks can be efficiently executed across DRAM hierarchy and their effect on overall application speedup. We also find that operations such as aggregates are more suitably executed on the CPU rather than PIM. Thus, we propose a cooperative query processing framework that capitalizes on both CPU and PIM strengths, where (i) the DRAM-based PIM block, with its massive parallelism, supports scan operations while (ii) CPU, with its flexible architecture, supports the rest of query execution. This allows us to utilize both PIM and CPU where appropriate and prevent dramatic changes to the overall system architecture. With these minimal modifications, our methodology enables us to faithfully perform end-to-end performance evaluations using established analytics benchmarks such as TPCH and star-schema benchmark (SSB). Our findings show that this novel mapping approach improves performance, delivering a 5.92x/6.5x speedup compared to a traditional schema and 3.03-4.05x speedup compared to a denormalized schema with 9-17% memory overhead, depending on the degree of partial denormalization. Further, we provide insights into query selectivity, memory overheads, and software optimizations in the context of PIM-based filtering, which better explain the behavior and performance of these systems across the benchmarks.

cs.AR↗

arXiv2015

Changes in porosity, permeability and surface area during rock dissolution: effects of mineralogical heterogeneity

Effects of heterogeneity of mineral distribution and reaction rate on the rock dissolution process are investigated using a pore-scale reactive transport model based on the lattice Boltzmann method. Coupled fluid flow, species transport, chemical reaction and solid structure alternation due to dissolution are simulated. Effects of mineral distributions and chemical heterogeneity on the dissolution behaviors and evolutions of hydrologic properties are studied under different reactive transport conditions. Simulation results show that the coupling between advection, diffusion and reaction as well as the mineralogical heterogeneity leads to complex reactive transport behaviors and complicated temporal evolutions of hydrologic properties including porosity, permeability and reactive surface. Diverse relationships between surface area and volume are predicted, which cannot be described by simple models such as the spherical-grain model. Porosity-permeability relationships also differ under different mineral distributions and reactive transport conditions. Simulation results indicate that it is extremely challenging to propose general relationships for hydrologic properties for dissolution of rocks with mineralogical heterogeneity, due to the complicated interactions between reactive transport and mineralogical heterogeneity.

physics.flu-dyn↗