Yiyang Gao | Searcharxiv

arXiv2026

HyperCut: Fast Inter-Layer Scheduling via Directed Hypergraph and Early Filtering

As deep neural networks (DNNs) continue to scale, inter-layer scheduling, which orchestrates the spatial allocation of compute resources and the temporal execution order across layers, has become a decisive factor in sustaining high utilization and energy efficiency on tiled accelerators. However, existing inter-layer schedulers defer cost feedback until a complete fine-grained intra-layer scheduling has been resolved. The resulting decoupled flow repeatedly explores sub-optimal or even infeasible inter-layer schedules, and the absence of early pruning during the inter-layer phase remains a critical bottleneck for design-space exploration (DSE) in DNN compilers. Our key observation is that the cost of an intra-layer scheduling can be tightly upper-bounded once the inter-layer cut fixes the sub-mesh shape, which lets us cost every inter-layer candidate without solving the intra-layer problem. Hence, we propose a hierarchical partitioning-and-mapping framework, HyperCut, that enables early filtering of inter-layer schedules based on hypergraph partitioning. Based on the directed hypergraph (DHG) abstraction of DNN, we introduce a unified representation, State, that jointly encodes the DHG partition, tile mesh allocation and tensor batch splitting. Thereby, partitioning and mapping are coupled into a union optimization object. For a DNN with N layers, the resulting theoretical design space is bounded by O(N), compared with O(9.899^N) for the state-of-the-art open-source scheduler SET. Across 10 evaluated cases, HyperCut achieves 2.0x performance improvement and 80.47% exploration time reduction over the SET baseline, measured by geometric mean.

cs.AR↗

arXiv2025

Exploiting the Uncertainty of the Longest Paths: Response Time Analysis for Probabilistic DAG Tasks

Parallel real-time systems (e.g., autonomous driving systems) often contain functionalities with complex dependencies and execution uncertainties, leading to significant timing variability which can be represented as a probabilistic distribution. However, existing timing analysis either produces a single conservative bound or suffers from severe scalability issues due to the exhaustive enumeration of every execution scenario. This causes significant difficulties in leveraging the probabilistic timing behaviours, resulting in sub-optimal design solutions. Modelling the system as a probabilistic directed acyclic graph (p-DAG), this paper presents a probabilistic response time analysis based on the longest paths of the p-DAG across all execution scenarios, enhancing the capability of the analysis by eliminating the need for enumeration. We first identify every longest path based on the structure of p-DAG and compute the probability of its occurrence. Then, the worst-case interfering workload is computed for each longest path, forming a complete probabilistic response time distribution with correctness guarantees. Experiments show that compared to the enumeration-based approach, the proposed analysis effectively scales to large p-DAGs with computation cost reduced by six orders of magnitude while maintaining a low deviation (1.04% on average and below 5% for most p-DAGs), empowering system design solutions with improved resource efficiency.

cs.DC↗