Topological-Insulator Heterophase Gate Stacks for Transistor Electrostatics
Conventional gate-stack scaling reduces dielectric thickness and increases permittivity while largely treating the position and electronic character of the gate-side screening boundary as fixed. Here we show that this boundary can be engineered by converting the surface of the topological insulator Bi\textsubscript{2}Se\textsubscript{3} into insulating high-$κ$ BiF\textsubscript{3}. Position-resolved calculations reveal a gap-opened immediate amorphous-BiF\textsubscript{3}/crystalline-Bi\textsubscript{2}Se\textsubscript{3} interface and a reconstructed gap-closed Bi\textsubscript{2}Se\textsubscript{3}-derived state in the adjacent subinterface layer, accompanied by a localized interfacial dipole. Capacitor measurements independently resolve a finite series response consistent with electronic compressibility at this boundary; this response lowers the nominal stack capacitance. Despite this capacitance penalty, MoS\textsubscript{2} transistors with closely matched BiF\textsubscript{3} thicknesses and a common BiF\textsubscript{3}/MoS\textsubscript{2} channel-side material interface exhibit near-thermionic-limit switching, negligible hysteresis and substantially weaker subthreshold drain-bias dependence than BiF\textsubscript{3}-only controls. These results identify the position and electronic character of the gate-side screening boundary as additional design variables for transistor electrostatics beyond nominal dielectric capacitance.