arXiv subjects

Yong-Xi Xiao

Publications and source records attributed to Yong-Xi Xiao.

5 recordsLinked to original sources

arXiv2026

Programmable spectral symmetries in an anisotropic quantum Rabi simulator

The quantum Rabi model captures fundamental aspects of light--matter interaction, where symmetry dictates both spectra and dynamics. Over the past years, experiments have explored many of its nonperturbative properties, but have mostly focused on the isotropic limit, where rotating and counterrotating processes are locked together, leaving the broader symmetry landscape largely unexplored. Here we realize a programmable anisotropic quantum Rabi model in a superconducting processor, with independent control of the rotating and counterrotating couplings $(g_1,g_2)$ and of a transverse bias $\varepsilon$. Continuous anisotropy tuning, combined with a duality mapping, gives access to the full parameter space from the Jaynes-Cummings to the anti-Jaynes-Cummings limits. In the deep-strong-coupling regime, we show that anisotropy reconstructs the spectrum and turns complete collapse-revival dynamics into incomplete revivals even near degeneracy. With adiabatic state preparation and joint tomography, we resolve an anisotropy-induced ground-state parity switch, a crossing that has no analogue in the isotropic model. We further observe selective tunnelling associated with hidden symmetry in biased Rabi models and track its anisotropic displacement within the same device. These results establish a controllable route to engineering nonperturbative light--matter Hamiltonians, where symmetry, spectrum, and dynamics can be programmed independently.

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arXiv2025

Direct Implementation of High-Fidelity Three-Qubit Gates for Superconducting Processor with Tunable Couplers

Three-qubit gates can be constructed using combinations of single-qubit and two-qubit gates, making their independent realization unnecessary. However, direct implementation of three-qubit gates reduces the depth of quantum circuits, streamlines quantum programming, and facilitates efficient circuit optimization, thereby enhancing overall performance in quantum computation. In this work, we propose and experimentally demonstrate a high-fidelity scheme for implementing a three-qubit controlled-controlled-Z (CCZ) gate in a flip-chip superconducting quantum processor with tunable couplers. This direct CCZ gate is implemented by simultaneously leveraging two tunable couplers interspersed between three qubits to enable three-qubit interactions, achieving an average final state fidelity of $97.94\%$ and a process fidelity of $93.54\%$. This high fidelity cannot be achieved through a simple combination of single- and two-qubit gate sequences from processors with similar performance levels. Our experiments also verify that multilayer direct implementation of the CCZ gate exhibits lower leakage compared to decomposed gate approaches. As a showcase, we utilize the CCZ gate as an oracle to implement the Grover search algorithm on three qubits, demonstrating high performance with the target probability amplitude significantly enhanced after two iterations. These results highlight the advantage of our approach, and facilitate the implementation of complex quantum circuits.

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arXiv2025

Flexible Readout and Unconditional Reset for Superconducting Multi-Qubit Processors with Tunable Purcell Filters

Achieving high-fidelity qubit readout and reset while preserving qubit coherence is essential for quantum error correction and other advanced quantum algorithms. Here, we design and experimentally demonstrate a scalable architecture employing frequency-tunable nonlinear Purcell filters, enabling flexible readout and fast unconditional reset of multiple superconducting qubits. Our readout protocol dynamically adjusts the effective linewidth of the readout resonator through a tunable Purcell filter, optimizing the signal-to-noise ratio during measurement while suppressing photon noise during idle periods. We achieve a readout fidelity of $99.3\%$ without any quantum-limited amplifier, even with a small dispersive shift. Moreover, by leveraging a reset channel formed via the adjacent coupling between the filter and the coupler, we realize unconditional qubit reset of both leakage-induced $|2\rangle$ and $|1\rangle$ states within 200 ns and reset of the $|1\rangle$ state alone within 75 ns, with error rates $\leq 1\%$. The filter also mitigates both photon-induced dephasing and the Purcell effect, thereby preserving qubit coherence. This scalable Purcell filter architecture shows exceptional performance in qubit readout, reset, and protection, marking it as a promising hardware component for advancing fault-tolerant quantum computing systems.

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arXiv2024

High-precision pulse calibration of tunable couplers for high-fidelity two-qubit gates in superconducting quantum processors

For superconducting quantum processors, stable high-fidelity two-qubit operations depend on precise flux control of the tunable coupler. However, the pulse distortion poses a significant challenge to the control precision. Current calibration methods, which often rely on microwave crosstalk or additional readout resonators for coupler excitation and readout, tend to be cumbersome and inefficient, especially when couplers only have flux control. Here, we introduce and experimentally validate a novel pulse calibration scheme that exploits the strong coupling between qubits and couplers, eliminating the need for extra coupler readout and excitation. Our method directly measures the short-time and long-time step responses of the coupler flux pulse transient, enabling us to apply predistortion to subsequent signals using fast Fourier transformation and deconvolution. This approach not only simplifies the calibration process but also significantly improves the precision and stability of the flux control. We demonstrate the efficacy of our method through the implementation of diabatic CZ and iSWAP gates with fidelities of $99.61\pm0.04\%$ and $99.82\pm0.02\%$, respectively, as well as a series of diabatic CPhase gates with high fidelities characterized by cross-entropy benchmarking. The consistency and robustness of our technique are further validated by the reduction in pulse distortion and phase error observed across multilayer CZ gates. These results underscore the potential of our calibration and predistortion method to enhance the performance of two-qubit gates in superconducting quantum processors.

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arXiv2023

Tunable Coupling Architectures with Capacitively Connecting Pads for Large-Scale Superconducting Multi-Qubit Processors

We have proposed and experimentally verified a tunable inter-qubit coupling scheme for large-scale integration of superconducting qubits. The key feature of the scheme is the insertion of connecting pads between qubit and tunable coupling element. In such a way, the distance between two qubits can be increased considerably to a few millimeters, leaving enough space for arranging control lines, readout resonators and other necessary structures. The increased inter-qubit distance provides more wiring space for flip-chip process and reduces crosstalk between qubits and from control lines to qubits. We use the term Tunable Coupler with Capacitively Connecting Pad (TCCP) to name the tunable coupling part that consists of a transmon coupler and capacitively connecting pads. With the different placement of connecting pads, different TCCP architectures can be realized. We have designed and fabricated a few multi-qubit devices in which TCCP is used for coupling. The measured results show that the performance of the qubits coupled by the TCCP, such as $T_1$ and $T_2$, was similar to that of the traditional transmon qubits without TCCP. Meanwhile, our TCCP also exhibited a wide tunable range of the effective coupling strength and a low residual ZZ interaction between the qubits by properly tuning the parameters on the design. Finally, we successfully implemented an adiabatic CZ gate with TCCP. Furthermore, by introducing TCCP, we also discuss the realization of the flip-chip process and tunable coupling qubits between different chips.

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