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Young Suh Song

Publications and source records attributed to Young Suh Song.

4 recordsLinked to original sources

Deep Learning to Automate Parameter Extraction and Model Fitting of Two-Dimensional Transistors

We present a deep learning approach to extract physical parameters (e.g., mobility, Schottky contact barrier height, defect profiles) of two-dimensional (2D) transistors from electrical measurements, enabling automated parameter extraction and technology computer-aided design (TCAD) fitting. To facilitate this task, we implement a simple data augmentation and pre-training approach by training a secondary neural network to approximate a physics-based device simulator. This method enables high-quality fits after training the neural network on electrical data generated from physics-based simulations of ~500 devices, a factor >40$\times$ fewer than other recent efforts. Consequently, fitting can be achieved by training on physically rigorous TCAD models, including complex geometry, self-consistent transport, and electrostatic effects, and is not limited to computationally inexpensive compact models. We apply our approach to reverse-engineer key parameters from experimental monolayer WS$_2$ transistors, achieving a median coefficient of determination ($R^2$) = 0.99 when fitting measured electrical data. We also demonstrate that this approach generalizes and scales well by reverse-engineering electrical data on high-electron-mobility transistors while fitting 35 parameters simultaneously. To facilitate future research on deep learning approaches for inverse transistor design, we have published our code and sample data sets online.

cs.LG

Scaling Nanoribbon Transistors with Monolayer Transition Metal Dichalcogenides

Nanoscale transistors require aggressive reduction of all channel dimensions: length, width, and thickness. While monolayer two-dimensional semiconductors (2DS) offer ultimate thickness scaling, good performance has largely been achieved only in micrometer-wide channels. Here, we demonstrate both $\it{n}$- and $\it{p}$-type nanoribbon transistors based on monolayer 2DS, fabricated using a multi-patterning process, reaching channel widths and lengths down to 25-30 nm. 'Anchored' contacts improve device yield, while nanoscale imaging, including tip-enhanced photoluminescence, reveals minimal edge degradation. The devices reach on-state currents up to 560, 420, and 130 $μ$A $μ$m$^{-1}$ at 1 V drain-to-source voltage for $\it{n}$-type MoS$_{2}$, WS$_{2}$, and $\it{p}$-type WSe$_{2}$, respectively, integrated with thin high-$κ$ dielectrics. These results surpass prior reports for single-gated nanoribbons, the WS$_{2}$ by over 100 times, even in normally off (enhancement-mode) transistors. Taken together, these findings suggest that top down patterned 2DS nanoribbons are promising building blocks for future nanosheet transistors.

cond-mat.mtrl-sci

High-current p-type transistors from precursor-engineered synthetic monolayer WSe$_2$

Monolayer tungsten diselenide (WSe$_2$) is a leading candidate for nanoscale complementary logic. However, high defect densities introduced during thin-film growth and device fabrication have limited p-type transistor performance. Here, we report a combined strategy of precursor-engineered chemical vapor deposition and damage-minimizing fabrication to overcome this limitation. By converting tungsten trioxide and residual oxyselenides into reactive suboxides before growth, and precisely regulating selenium delivery during deposition, we synthesize uniform, centimeter-scale monolayer WSe$_2$ films with charged defect densities as low as $5 \times 10^{9}$ cm$^{-2}$. Transistors fabricated from these films achieve record p-type on-state current up to $888 μ$A$\cdotμ$m$^{-1}$ at $V_{\mathrm{DS}}=-1$ V, matching leading n-type devices. This leap in material quality closes the p-type performance gap without exotic doping or contact materials, marking a critical step towards complementary two-dimensional semiconductor circuits.

cond-mat.mtrl-sci

High-field Breakdown and Thermal Characterization of Indium Tin Oxide Transistors

Amorphous oxide semiconductors are gaining interest for logic and memory transistors compatible with low-temperature fabrication. However, their low thermal conductivity and heterogeneous interfaces suggest that their performance may be severely limited by self-heating, especially at higher power and device densities. Here, we investigate the high-field breakdown of ultrathin (~4 nm) amorphous indium tin oxide (ITO) transistors with scanning thermal microscopy (SThM) and multiphysics simulations. The ITO devices break irreversibly at channel temperatures of ~180 °C and ~340 °C on SiO${_2}$ and HfO${_2}$ substrates, respectively, with failure primarily caused by thermally-induced compressive strain near the device contacts. Combining SThM measurements with simulations allows us to estimate a thermal boundary conductance (TBC) of 35 ${\pm}$ 12 MWm${^-}$${^2}$K${^-}$${^1}$ for ITO on SiO${_2}$, and 51 ${\pm}$ 14 MWm${^-}$${^2}$K${^-}$${^1}$ for ITO on HfO${_2}$. The latter also enables significantly higher breakdown power due to better heat dissipation and closer thermal expansion matching. These findings provide insights into the thermo-mechanical limitations of indium-based amorphous oxide transistors, which are important for more reliable and high-performance logic and memory applications.

physics.app-ph