arXiv subjects

Yu-Hung Liao

Publications and source records attributed to Yu-Hung Liao.

3 recordsLinked to original sources

arXiv2021

Ferroelectric HfO$_2$ Memory Transistors with High-$κ$ Interfacial Layer and Write Endurance Exceeding $10^{10}$ Cycles

We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon channel with endurance exceeding $10^{10}$ cycles. The ferroelectric transistors (FeFETs) incorporate a high-$κ$ interfacial layer (IL) of thermally grown silicon nitride (SiN$_x$) and a thin 4.5 nm layer of Zr-doped FE-HfO$_2$ on a $\sim$30 nm SOI channel. The device shows a $\sim$ 1V memory window in a DC sweep of just $\pm$ 2.5V, and can be programmed and erased with voltage pulses of $V_G= \pm$ 3V at a pulse width of 250 ns. The device also shows very good retention behavior. These results indicate that appropriate engineering of the IL layer could substantially improve FeFET device performance and reliability.

physics.app-ph↗

arXiv2020

Negative Capacitance Enables FinFET Scaling Beyond 3nm Node

A comprehensive study of the scaling of negative capacitance FinFET (NC-FinFET) is conducted with TCAD. We show that the NC-FinFET can be scaled to "2.1nm node" and almost "1.5nm node" that comes two nodes after the industry "3nm node," which has 16nm Lg and is the last FinFET node according to the International Roadmap for Devices and Systems (IRDS). In addition, for the intervening nodes, NC-FinFET can meet IRDS Ion and Ioff target at target-beating VDD. The benefits of negative capacitance (NC) include improved subthreshold slope (SS), drain-induced barrier lowering (DIBL), Vt roll-off, transconductance over Id (Gm/Id), output conductance over Id (Gd/Id), and lower VDD. Further scaling may be achieved by improving capacitance matching between ferroelectric (FE) and dielectric (DE).

physics.app-ph↗

arXiv2020

Anomalous Subthreshold Behaviors in Negative Capacitance Transistors

Recent measurements on ultra-thin body Negative Capacitance Field Effect Transistors have shown subthreshold behaviors that are not expected in a classical MOSFET. Specifically, subthreshold swing was found to decrease with increased gate bias in the subthreshold region for devices measured over multiple gate lengths down to 30 nm. In addition, improvement in the subthreshold swing relative to control devices showed a non-monotonic dependence on the gate length. In this paper, using a Landau-Khanatnikov ferroelectric gate stack model calibrated with measured Capacitance-Voltage, we show that both these anomalous behaviors can be quantitatively reproduced with TCAD simulations.

physics.app-ph↗