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Yuan-Mau Lee

Publications and source records attributed to Yuan-Mau Lee.

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Scaling Nanoribbon Transistors with Monolayer Transition Metal Dichalcogenides

Nanoscale transistors require aggressive reduction of all channel dimensions: length, width, and thickness. While monolayer two-dimensional semiconductors (2DS) offer ultimate thickness scaling, good performance has largely been achieved only in micrometer-wide channels. Here, we demonstrate both $\it{n}$- and $\it{p}$-type nanoribbon transistors based on monolayer 2DS, fabricated using a multi-patterning process, reaching channel widths and lengths down to 25-30 nm. 'Anchored' contacts improve device yield, while nanoscale imaging, including tip-enhanced photoluminescence, reveals minimal edge degradation. The devices reach on-state currents up to 560, 420, and 130 $μ$A $μ$m$^{-1}$ at 1 V drain-to-source voltage for $\it{n}$-type MoS$_{2}$, WS$_{2}$, and $\it{p}$-type WSe$_{2}$, respectively, integrated with thin high-$κ$ dielectrics. These results surpass prior reports for single-gated nanoribbons, the WS$_{2}$ by over 100 times, even in normally off (enhancement-mode) transistors. Taken together, these findings suggest that top down patterned 2DS nanoribbons are promising building blocks for future nanosheet transistors.

cond-mat.mtrl-sci

High-field Breakdown and Thermal Characterization of Indium Tin Oxide Transistors

Amorphous oxide semiconductors are gaining interest for logic and memory transistors compatible with low-temperature fabrication. However, their low thermal conductivity and heterogeneous interfaces suggest that their performance may be severely limited by self-heating, especially at higher power and device densities. Here, we investigate the high-field breakdown of ultrathin (~4 nm) amorphous indium tin oxide (ITO) transistors with scanning thermal microscopy (SThM) and multiphysics simulations. The ITO devices break irreversibly at channel temperatures of ~180 °C and ~340 °C on SiO${_2}$ and HfO${_2}$ substrates, respectively, with failure primarily caused by thermally-induced compressive strain near the device contacts. Combining SThM measurements with simulations allows us to estimate a thermal boundary conductance (TBC) of 35 ${\pm}$ 12 MWm${^-}$${^2}$K${^-}$${^1}$ for ITO on SiO${_2}$, and 51 ${\pm}$ 14 MWm${^-}$${^2}$K${^-}$${^1}$ for ITO on HfO${_2}$. The latter also enables significantly higher breakdown power due to better heat dissipation and closer thermal expansion matching. These findings provide insights into the thermo-mechanical limitations of indium-based amorphous oxide transistors, which are important for more reliable and high-performance logic and memory applications.

physics.app-ph