PowerFlow-DNN: Compiler-Directed Fine-Grained Power Orchestration for End-to-End Edge AI Inference
Edge AI systems operate under stringent energy and volume constraints, demanding extreme efficiency on limited battery capacity, with requirements worsening as intelligent capabilities advance. Prior work suggests fine-grained power orchestration through DVFS and power gating significantly improves efficiency critical to meeting such constraints, but introduces new challenges. We observe that layer-level approaches incur unintended overheads due to inter-layer coupling of power-control decisions, and jointly managing these mechanisms under limited voltage rails and transition overheads leads to a rapidly growing combinatorial schedule space. We propose PowerFlow-DNN, a compiler-directed framework for end-to-end power-state orchestration in ultra-low-power accelerators. By constructing a rigorous problem formulation for deadline-constrained, real-time, periodic inference as a unified inter-layer power-scheduling problem, our framework discovers energy-minimal power-state schedules while accounting for inter-layer impacts. We evaluate the framework on a DNN accelerator VLSI implementation in TSMC 40nm technology. Across representative edge networks, our approach discovers near-optimal solutions and achieves energy within 0.04\% of the exact ILP oracle, reducing energy by up to 48\% compared to an aggressive baseline without power orchestration, while reasoning over a combinatorial schedule space of over $10^{160}$ possible power-state assignments, yet operating on a structured layered state graph that enables efficient optimization, achieving up to 2.14$\times$ solver speedup via lightweight pruning.