arXiv subjects

Yubiao Luo

Publications and source records attributed to Yubiao Luo.

4 recordsLinked to original sources

arXiv2026

A neuromorphic vision system for open-world visual intelligence

Time-efficient and robust visual intelligence remains a critical challenge in unstructured open-world environments, yet current approaches often rely on computationally intensive neural architectures or task-specific sensors with limited versatility. Inspired by biological vision and information bottleneck theory, we report a neuromorphic vision system that performs task-oriented visual intelligence through an information distillation strategy (named as task traction mechanism) implemented on hardware. The system integrates a polarization-sensitive imager with a resistive random-access memory (RRAM) array to progressively distill task-relevant information via light field selection, region of interest extraction, and target anticipation. The neuromorphic vision system conducts visual tasks within an execution time of 193 μs. Evaluation across eight challenging open-world scenarios shows accuracy improvements of 25.54%, 37.73%, and 36.10% for object tracking, object segmentation, and trajectory prediction, respectively, together with an average 30.6-fold reduction in latency relative to state-of-the-art solutions.

eess.IV↗

arXiv2025

First Demonstration of Second-order Training of Deep Neural Networks with In-memory Analog Matrix Computing

Second-order optimization methods, which leverage curvature information, offer faster and more stable convergence than first-order methods such as stochastic gradient descent (SGD) and Adam. However, their practical adoption is hindered by the prohibitively high cost of inverting the second-order information matrix, particularly in large-scale neural network training. Here, we present the first demonstration of a second-order optimizer powered by in-memory analog matrix computing (AMC) using resistive random-access memory (RRAM), which performs matrix inversion (INV) in a single step. We validate the optimizer by training a two-layer convolutional neural network (CNN) for handwritten letter classification, achieving 26% and 61% fewer training epochs than SGD with momentum and Adam, respectively. On a larger task using the same second-order method, our system delivers a 5.88x improvement in throughput and a 6.9x gain in energy efficiency compared to state-of-the-art digital processors. These results demonstrate the feasibility and effectiveness of AMC circuits for second-order neural network training, opening a new path toward energy-efficient AI acceleration.

cs.ET↗

arXiv2025

Modeling Closed-loop Analog Matrix Computing Circuits with Interconnect Resistance

Analog matrix computing (AMC) circuits based on resistive random-access memory (RRAM) have shown strong potential for accelerating matrix operations. However, as matrix size grows, interconnect resistance increasingly degrades computational accuracy and limits circuit scalability. Modeling and evaluating these effects are therefore critical for developing effective mitigation strategies. Traditional SPICE (Simulation Program with Integrated Circuit Emphasis) simulators, which rely on modified nodal analysis, become prohibitively slow for large-scale AMC circuits due to the quadratic growth of nodes and feedback connections. In this work, we model AMC circuits with interconnect resistance for two key operations-matrix inversion (INV) and eigenvector computation (EGV), and propose fast solving algorithms tailored for each case. The algorithms exploit the sparsity of the Jacobian matrix, enabling rapid and accurate solutions. Compared to SPICE, they achieve several orders of magnitude acceleration while maintaining high accuracy. We further extend the approach to open-loop matrix-vector multiplication (MVM) circuits, demonstrating similar efficiency gains. Finally, leveraging these fast solvers, we develop a bias-based compensation strategy that reduces interconnect-induced errors by over 50% for INV and 70% for EGV circuits. It also reveals the scaling behavior of the optimal bias with respect to matrix size and interconnect resistance.

cs.ET↗

arXiv2024

BlockAMC: Scalable In-Memory Analog Matrix Computing for Solving Linear Systems

Recently, in-memory analog matrix computing (AMC) with nonvolatile resistive memory has been developed for solving matrix problems in one step, e.g., matrix inversion of solving linear systems. However, the analog nature sets up a barrier to the scalability of AMC, due to the limits on the manufacturability and yield of resistive memory arrays, non-idealities of device and circuit, and cost of hardware implementations. Aiming to deliver a scalable AMC approach for solving linear systems, this work presents BlockAMC, which partitions a large original matrix into smaller ones on different memory arrays. A macro is designed to perform matrix inversion and matrix-vector multiplication with the block matrices, obtaining the partial solutions to recover the original solution. The size of block matrices can be exponentially reduced by performing multiple stages of divide-and-conquer, resulting in a two-stage solver design that enhances the scalability of this approach. BlockAMC is also advantageous in alleviating the accuracy issue of AMC, especially in the presence of device and circuit non-idealities, such as conductance variations and interconnect resistances. Compared to a single AMC circuit solving the same problem, BlockAMC improves the area and energy efficiency by 48.83% and 40%, respectively.

cs.AR↗