Yuman Cai | Searcharxiv

arXiv2026

Beam Test Characterization of Silicon Microstrip Detector Flight-Model Ladders for the AMS-02 Upgrade

The AMS-02 experiment plans to install a new silicon microstrip tracker layer (Layer-0) on top of the existing detector, increasing the cosmic-ray acceptance by a factor of 3. Layer-0 employs a design in which multiple silicon microstrip detectors (SSDs) are connected in series to form long detector ladders. We present a detailed performance study of the flight-model ladders using a 350~GeV mixed hadron beam at the CERN SPS. The study focuses on the following aspects: (i) the performance of ladders with different numbers of SSDs, for which the intrinsic spatial resolution at normal incidence varies from $9.5~\mu\mathrm{m}$ to $11.4~\mu\mathrm{m}$ for ladders composed of 8 to 12 SSDs; (ii) the response consistency for particles impacting on the \emph{Head} and \emph{Tail} regions of the ladder; and (iii) the dependence of the detector performance on the particle incidence angle.

physics.ins-det↗

arXiv2026

Design and First Results of COFFEE3: A 55nm HVCMOS Pixel Sensor Prototype for High-Energy Physics Applications

Motivated by the stringent requirements of the Upstream Pixel (UP) tracker in the LHCb Upgrade II and the Inner Tracking detector (ITK) of the Circular Electron Positron Collider, the COFFEE series of pixel sensor chips have been developed using a 55nm High-Voltage CMOS (HVCMOS) process. The primary objective is to achieve a time resolution of a few nanoseconds under a hit density of up to 100 MHz/cm$^2$, while maintaining fine spatial resolution ($\sim$10 $\mu$m) and reasonable power consumption ($<$200 mW/cm$^2$). Building on the process validation of the COFFEE2 prototype, this work presents the design and preliminary test results of COFFEE3-a prototype integrating two distinct readout architectures. Architecture 1, tailored for the current triple-well process, adopts NMOS-only in-pixel circuitry and innovative column-level readout to handle high hit densities. The time walk of pixel-level signal is controlled within 10 ns, and the Time of Arrival (TOA) and Time over Threshold (TOT) are measured with a system clock with the period of 25 ns in peripheral circuits. Architecture 2, developed for future possible processes with p-type buried layer isolation, features pixel-level time measurement and storage. A chip-level Time-to-Digital Converter (TDC) is used and the part of Voltage-Controlled Delay Line (VCDL) is copied in each pixel to get a high time resolution. The TOA resolution is estimated to be 4.2 ns and the TOT resolution 8.4 ns. COFFEE3, with a layout size of 3$\times$4 mm$^2$, was manufactured and has undergone preliminary tests. Charge injection tests for analog circuits, and laser tests for full readout chains, confirm that both architectures operate as expected. Next step work will focus on characterizing key performance such as the timing resolution, radiation hardness, and tracking performance of minimum ionising particles.

physics.ins-det↗