arXiv subjects

Yuriy V. Pershin

Publications and source records attributed to Yuriy V. Pershin.

At least 19 recordsLinked to original sources

arXiv2025

Minimizing energy dissipation during programming of resistive switching memory devices using their dynamical attractor states

Under certain conditions, applying a sequence of voltage pulses of alternating polarities across a resistive switching memory device induces a finite number of fixed-point attractors in its time-averaged dynamics, known as dynamical attractors. Remarkably, dynamical attractors can be used to program analog values into the device state without supervision. Because different pulse sequences can produce the same trajectory solution for the state in the phase space, there is strong potential for optimization, particularly regarding the energy cost of the programming phase, which this study addresses. The proposed theory-based energy minimization strategy is applied to the voltage threshold adaptive memristor (VTEAM) model, which is known for its predictive capability and adaptability in fitting a large number of resistive switching memory devices. The optimization design crafts ad-hoc pulse sequences that minimize the energy required to program the device into a desired dynamical attractor. The theoretical approach is also extended to cover situations where a fast programming scheme should be adopted to serve time-critical electronics applications.

cond-mat.mes-hall↗

arXiv2025

On the solvable-unsolvable transition due to noise-induced chaos in digital memcomputing

Digital memcomputing machines (DMMs) have been designed to solve complex combinatorial optimization problems. Since DMMs are fundamentally classical dynamical systems, their ordinary differential equations (ODEs) can be efficiently simulated on modern computers. This provides a unique platform to study their performance under various conditions. An aspect that has received little attention so far is how their performance is affected by the numerical errors in the solution of their ODEs and the physical noise they would be naturally subject to if built in hardware. Here, we analyze these two aspects in detail by varying the integration time step (numerical noise) and adding stochastic perturbations (physical noise) into the equations of DMMs. We are particularly interested in understanding how noise induces a chaotic transition that marks the shift from successful problem-solving to failure in these systems. Our study includes an analysis of power spectra and Lyapunov exponents depending on the noise strength. The results reveal a correlation between the instance solvability and the sign of the ensemble averaged mean largest Lyapunov exponent. Interestingly, we find a regime in which DMMs with positive mean largest Lyapunov exponents still exhibit solvability. Furthermore, the power spectra provide additional information about our system by distinguishing between regular behavior (peaks) and chaotic behavior (broadband spectrum). Therefore, power spectra could be utilized to control whether a DMM operates in the optimal dynamical regime. Overall, we find that the qualitative effects of numerical and physical noise are mostly similar, despite their fundamentally different origin.

nlin.CD↗

arXiv2025

Low-Power Control of Resistance Switching Transitions in First-Order Memristors

In many cases, the behavior of physical memristive devices can be relatively well captured by using a single internal state variable. This study investigates the low-power control of first-order memristive devices to derive the most energy-efficient protocols for programming their resistances. A unique yet general approach to optimizing the switching transitions in devices of this kind is introduced. For pedagogical purposes, without loss of generality, the proposed control paradigm is applied to a couple of differential algebraic equation sets for voltage-controlled devices, specifically Kvatinsky's Voltage ThrEshold Adaptive Memristor mathematical description and Miranda's and Sune's dynamic balance model. It is demonstrated that, depending upon intrinsic physical properties of the device, captured in the model formulas and parameter setting, and upon constraints on programming time and voltages, the optimal protocol for either of the two switching scenarios may require the application of a single square voltage pulse of height set to a certain level within the admissible range across a fraction or entire given programming time interval, or of some more involved voltage stimulus of unique polarity, including analogue continuous waveforms that can be approximated by trains of square voltage pulses of different heights, over the entire programming time interval. The practical implications of these research findings are significant, as the development of energy-efficient protocols to program memristive devices, resolving the so-called voltage-time dilemma in the device physics community, is a subject under intensive and extensive studies across the academic community and industry.

cs.ET↗

arXiv2025

EGaIn tube memristors offer reliable switching on a biological time scale

Memristive devices have been considered promising candidates for nature-inspired computing and in-memory information processing. However, experimental devices developed to date typically show significant variability and function at different time scales than biological neurons and synapses. This study presents a new kind of memristive device comprised of liquid-metal eutectic gallium indium (EGaIn) contained within a mm-scale tube that operates via a bulk, voltage-dependent switching mechanism and exhibits distinct unipolar resistive switching characteristics that occur on a biological time scale (tens of milliseconds). The switching mechanism involves voltage-controlled growth and dissolution of an oxide layer on the surface of the liquid metal in contact with an aqueous electrolyte. Through comprehensive measurements on many devices, we observed remarkably consistent cycle-to-cycle behavior and uniformity in the voltage-controlled memristance. We present our findings, which also include an experimental demonstration of logic gates utilizing EGaIn tube memristors. Furthermore, we observe both accelerated and decelerated switching behaviors and identify signatures indicative of a fractional dynamic response.

physics.app-ph↗

arXiv2025

Low-power switching of memristors exhibiting fractional-order dynamics

In this conference contribution, we present some initial results on switching memristive devices exhibiting fractional-order behavior using current pulses. In our model, it is assumed that the evolution of a state variable follows a fractional-order differential equation involving a Caputo-type derivative. A study of Joule losses demonstrates that the best switching strategy minimizing these losses depends on the fractional derivative's order and the power exponent in the equation of motion. It is found that when the order of the fractional derivative exceeds half of the power exponent, the best approach is to employ a wide pulse. Conversely, when this condition is not met, Joule losses are minimized by applying a zero current followed by a narrow current pulse of the highest allowable amplitude. These findings are explored further in the context of multi-pulse control. Our research lays the foundation for the advancement of the next generation of energy-efficient neuromorphic computing architectures that more closely mimic their biological counterparts.

cs.ET↗

arXiv2024

Accurate modeling of continuous-time SAT solvers in SPICE

Recently, there has been an increasing interest in employing dynamical systems as solvers of NP-complete problems. In this paper, we present accurate implementations of two continuous-time dynamical solvers, known in the literature as analog SAT and digital memcomputing, using advanced numerical integration algorithms of SPICE circuit simulators. For this purpose, we have developed Python scripts that convert Boolean satisfiability (SAT) problems into electronic circuits representing the analog SAT and digital memcomputing dynamical systems. Our Python scripts process conjunctive normal form (CNF) files and create netlists that can be directly imported into LTspice. We explore the SPICE implementations of analog SAT and digital memcomputing solvers by applying these to a selected set of problems and present some interesting and potentially useful findings related to digital memcomputing and analog SAT. In this work, we also introduce networks of continuous-time solvers with potential applications extending beyond the solution of Boolean satisfiability problems.

cs.ET↗

arXiv2024

Reduction of Joule Losses in Memristive Switching Using Optimal Control

This study investigates strategies for minimizing Joule losses in resistive random access memory (ReRAM) cells, which are also referred to as memristive devices. Typically, the structure of ReRAM cells involves a nanoscale layer of resistance-switching material sandwiched between two metal electrodes. The basic question that we ask is what is the optimal driving protocol to switch a memristive device from one state to another. In the case of ideal memristors, in the most basic scenario, the optimal protocol is determined by solving a variational problem without constraints with the help of the Euler-Lagrange equation. In the case of memristive systems, for the same situation, the optimal protocol is found using the method of Lagrange multipliers. We demonstrate the advantages of our approaches through specific examples and compare our results with those of switching with constant voltage or current. Our findings suggest that voltage or current control can be used to reduce Joule losses in emerging memory devices.

cs.ET↗

arXiv2024

Fully parallel implementation of digital memcomputing on FPGA

We present a fully parallel digital memcomputing solver implemented on a field-programmable gate array (FPGA) board. For this purpose, we have designed an FPGA code that solves the ordinary differential equations associated with digital memcomputing in parallel. A feature of the code is the use of only integer-type variables and integer constants to enhance optimization. Consequently, each integration step in our solver is executed in 96~ns. This method was utilized for difficult instances of the Boolean satisfiability (SAT) problem close to a phase transition, involving up to about 150 variables. Our results demonstrate that the parallel implementation reduces the scaling exponent by about 1 compared to a sequential C++ code on a standard computer. Additionally, compared to C++ code, we observed a time-to-solution advantage of about three orders of magnitude. Given the limitations of FPGA resources, the current implementation of digital memcomputing will be especially useful for solving compact but challenging problems.

cs.ET↗

arXiv2024

Acceleration of digital memcomputing by jumps

In this article, we present the potential benefits of incorporating jumps into the dynamics of digital memcomputing machines (DMMs), which have been developed to address complex optimization problems. We illustrate the potential speed improvement of a DMM solver with jumps over an unmodified DMM solver by solving Boolean satisfiability (SAT) problems of different complicatedness. Our findings suggest that jumps can modify scaling exponents and improve solving times by up to 75 %. Interestingly, the advantages of jumps can be seen in cases where the size of the jump is so large that otherwise the continuous dynamics of voltage variables becomes almost binary.

cs.ET↗

arXiv2024

Roadmap for Unconventional Computing with Nanotechnology

In the "Beyond Moore's Law" era, with increasing edge intelligence, domain-specific computing embracing unconventional approaches will become increasingly prevalent. At the same time, adopting a variety of nanotechnologies will offer benefits in energy cost, computational speed, reduced footprint, cyber resilience, and processing power. The time is ripe for a roadmap for unconventional computing with nanotechnologies to guide future research, and this collection aims to fill that need. The authors provide a comprehensive roadmap for neuromorphic computing using electron spins, memristive devices, two-dimensional nanomaterials, nanomagnets, and various dynamical systems. They also address other paradigms such as Ising machines, Bayesian inference engines, probabilistic computing with p-bits, processing in memory, quantum memories and algorithms, computing with skyrmions and spin waves, and brain-inspired computing for incremental learning and problem-solving in severely resource-constrained environments. These approaches have advantages over traditional Boolean computing based on von Neumann architecture. As the computational requirements for artificial intelligence grow 50 times faster than Moore's Law for electronics, more unconventional approaches to computing and signal processing will appear on the horizon, and this roadmap will help identify future needs and challenges. In a very fertile field, experts in the field aim to present some of the dominant and most promising technologies for unconventional computing that will be around for some time to come. Within a holistic approach, the goal is to provide pathways for solidifying the field and guiding future impactful discoveries.

cs.ET↗

arXiv2023

Hardware implementation of digital memcomputing on small-size FPGAs

Memcomputing is a novel computing paradigm beyond the von-Neumann one. Its digital version is designed for the efficient solution of combinatorial optimization problems, which emerge in various fields of science and technology. Previously, the performance of digital memcomputing machines (DMMs) was demonstrated using software simulations of their ordinary differential equations. Here, we present the first hardware realization of a DMM algorithm on a low-cost FPGA board. In this demonstration, we have implemented a Boolean satisfiability problem solver. To optimize the use of hardware resources, the algorithm was partially parallelized. The scalability of the present implementation is explored and our FPGA-based results are compared to those obtained using a python code running on a traditional (von-Neumann) computer, showing one to two orders of magnitude speed-up in time to solution. This initial small-scale implementation is projected to state-of-the-art FPGA boards anticipating further advantages of the hardware realization of DMMs over their software emulation.

cs.ET↗

arXiv2023

Electromechanical memcapacitive neurons for energy-efficient spiking neural networks

In this article, we introduce a new nanoscale electromechanical device -- a leaky memcapacitor -- and show that it may be useful for the hardware implementation of spiking neurons. The leaky memcapacitor is a movable-plate capacitor that becomes quite conductive when the plates come close to each other. The equivalent circuit of the leaky memcapacitor involves a memcapacitive and memristive system connected in parallel. In the leaky memcapacitor, the resistance and capacitance depend on the same internal state variable, which is the displacement of the movable plate. We have performed a comprehensive analysis showing that several spiking types observed in biological neurons can be implemented with the leaky memcapacitor. Significant attention is paid to the dynamic properties of the model. As in leaky memcapacitors the capacitive and leaking resistive functionalities are implemented naturally within the same device structure, their use will simplify the creation of spiking neural networks.

cs.ET↗

arXiv2022

Custodial chiral symmetry in a Su-Schrieffer-Heeger electrical circuit with memory

Custodial symmetries are common in the Standard Model of particle physics. They arise when quantum corrections to a parameter are proportional to the parameter itself. Here, we show that a custodial symmetry of the chiral type is also present in a classical Su-Schrieffer-Heeger (SSH) electrical circuit with memory (memcircuit). In the absence of memory, the SSH circuit supports a symmetry-protected topological edge state. Memory induces nonlinearities that break chiral symmetry explicitly and spreads the state across the circuit. However, the resulting state is still protected against perturbations by the ensuing custodial chiral symmetry. These predictions can be verified experimentally and demonstrate the interplay between symmetry and memory.

cond-mat.mes-hall↗

arXiv2017

Surface effects on ionic Coulomb blockade in nanometer-size pores

Ionic Coulomb blockade in nanopores is a phenomenon that shares some similarities but also differences with its electronic counterpart. Here, we investigate extensively this phenomenon using all-atom molecular dynamics of ionic transport through nanopores of about one nanometer in diameter and up to several nanometers in length. Our goal is to better understand the role of atomic roughness and structure of the pore walls in the ionic Coulomb blockade. Our numerical results reveal the following general trends. First, the nanopore selectivity changes with its diameter, and the nanopore position in the membrane influences the current strength. Second, the ionic transport through the nanopore takes place in a hopping-like fashion over a set of discretized states caused by local electric fields due to membrane atoms. In some cases, this creates a slow-varying "crystal-like" structure of ions inside the nanopore. Third, while at a given voltage, the resistance of the nanopore depends on its length, the slope of this dependence appears to be independent of the molarity of ions. An effective kinetic model that captures the ionic Coulomb blockade behavior observed in MD simulations is formulated.

cond-mat.mes-hall↗

arXiv2016

Qubit-based memcapacitors and meminductors

It is shown that superconducting charge and phase qubits are quantum versions of memory capacitive and inductive systems, respectively. We demonstrate that such quantum memcapacitive and meminductive devices offer remarkable and rich response functionalities. In particular, when subjected to periodic input, qubit-based memcapacitors and meminductors exhibit unusual hysteresis curves. Our work not only extends the set of known memcapacitive and meminductive systems to qubit-based quantum devices but also highlights their unique properties potentially useful for future technological applications.

cond-mat.mes-hall↗

arXiv2016

Memristive Sisyphus circuit for clock signal generation

Frequency generators are widely used in electronics. Here, we report the design and experimental realization of a memristive frequency generator employing a unique combination of only digital logic gates, a single-supply voltage and a realistic threshold-type memristive device. In our circuit, the oscillator frequency and duty cycle are defined by the switching characteristics of the memristive device and external resistors. We demonstrate the circuit operation both experimentally, using a memristor emulator, and theoretically, using a model memristive device with threshold. Importantly, nanoscale realizations of memristive devices offer small-size alternatives to conventional quartz-based oscillators. In addition, the suggested approach can be used for mimicking some cyclic (Sisyphus) processes in nature, such as "dripping ants" or drops from leaky faucets.

cond-mat.mes-hall↗

arXiv2015

Memcomputing with membrane memcapacitive systems

We show theoretically that networks of membrane memcapacitive systems -- capacitors with memory made out of membrane materials -- can be used to perform a complete set of logic gates in a massively parallel way by simply changing the external input amplitudes, but not the topology of the network. This polymorphism is an important characteristic of memcomputing (computing with memories) that closely reproduces one of the main features of the brain. A practical realization of these membrane memcapacitive systems, using, e.g., graphene or other 2D materials, would be a step forward towards a solid-state realization of memcomputing with passive devices.

cs.ET↗

arXiv2014

Dynamic Computing Random Access Memory

The present von Neumann computing paradigm involves a significant amount of information transfer between a central processing unit (CPU) and memory, with concomitant limitations in the actual execution speed. However, it has been recently argued that a different form of computation, dubbed memcomputing [Nature Physics, 9, 200-202 (2013)] and inspired by the operation of our brain, can resolve the intrinsic limitations of present day architectures by allowing for computing and storing of information on the same physical platform. Here we show a simple and practical realization of memcomputing that utilizes easy-to-build memcapacitive systems. We name this architecture Dynamic Computing Random Access Memory (DCRAM). We show that DCRAM provides massively-parallel and polymorphic digital logic, namely it allows for different logic operations with the same architecture, by varying only the control signals. In addition, by taking into account realistic parameters, its energy expenditures can be as low as a few fJ per operation. DCRAM is fully compatible with CMOS technology, can be realized with current fabrication facilities, and therefore can really serve as an alternative to the present computing technology.

cs.ET↗