arXiv subjects

Yusuf Leblebici

Publications and source records attributed to Yusuf Leblebici.

6 recordsLinked to original sources

arXiv2021

Modeling Electrical Resistance Drift with Ultrafast Saturation of OTS Selectors

Crossbar array architecture is an essential design element for densely connected Non-Volatile Memory(NVM) applications. To overcome intrinsic sneak current problem of crossbar arrays, each memory unit is serially attached to a selector unit with highly nonlinear current-voltage (I-V) characteristics. Recently, Ovonic Threshold Switching (OTS) materials are preferred as selectors due to their fabrication compatibility with PRAM, MRAM or ReRAM technologies; however, OTS selectors suffer from the temporal drift of its threshold voltage. First, based on Poole-Frenkel conduction, we present time and temperature dependent model that predicts temporally evolving I-V characteristics,including threshold voltage of OTS selectors. Second, we report an ultrafast saturation ($\sim 10^3$ seconds) of the drift and extend the model to predict the time of drift saturation. Our model shows excellent agreement with OTS devices fabricated with 8 nm technology node at 25°C and 85°C ambient temperatures. The proposed model plays a significant role in understanding OTS device internals and the development of reliable threshold voltage jump table.

physics.app-ph↗

arXiv2019

Neuromorphic computing with multi-memristive synapses

Neuromorphic computing has emerged as a promising avenue towards building the next generation of intelligent computing systems. It has been proposed that memristive devices, which exhibit history-dependent conductivity modulation, could efficiently represent the synaptic weights in artificial neural networks. However, precise modulation of the device conductance over a wide dynamic range, necessary to maintain high network accuracy, is proving to be challenging. To address this, we present a multi-memristive synaptic architecture with an efficient global counter-based arbitration scheme. We focus on phase change memory devices, develop a comprehensive model and demonstrate via simulations the effectiveness of the concept for both spiking and non-spiking neural networks. Moreover, we present experimental results involving over a million phase change memory devices for unsupervised learning of temporal correlations using a spiking neural network. The work presents a significant step towards the realization of large-scale and energy-efficient neuromorphic computing systems.

cs.ET↗

arXiv2018

Direct Reconstruction of Saturated Samples in Band-Limited OFDM Signals

Given a set of samples, a few of them being possibly saturated, we propose an efficient algorithm in order to cancel saturation while reconstructing band-limited signals. Our method satisfies a minimum-loss constraint and relies on sinc-related bases. It involves matrix inversion and is a direct, non-iterative approach. It consists of two main steps: (i) regression, to estimate the expansion coefficients of the signal model; (ii) interpolation, to restore an estimated value for those samples that are saturated. Because the proposed method is free from tuning parameters, it is hardware-friendly and we expect that it will be particularly useful in the context of orthogonal frequency-division multiplexing. There, the high peak-to-average power ratio of the transmitted signal results in a challenging decoding stage in the presence of saturation, which causes significant decoding errors due to the nonlinearity of amplifiers and receivers, ultimately resulting in band distortion and information loss. Our experiments on realistic simulations confirm that our proposed reconstruction of the saturated samples can significantly reduce transmission errors in modern high-throughput digital-communication receivers.

eess.SP↗

arXiv2016

High-frequency, scaled MoS2 transistors

The interest in MoS2 for radio-frequency (RF) application has recently increased. However, little is known on the scaling behavior of transistors made from MoS2 for RF applications, which is important for establishing performance limits for electronic circuits based on 2D semiconductors on flexible and rigid substrates. Here, we present a systematic study of top-gated trilayer MoS2 RF transistors with gate lengths scaled down to 70 and 40 nm. In addition, by introducing edge-contacted injection of electrons in trilayer MoS2 devices, we decrease the contact resistance and as a result obtain the highest cutoff frequency of 6 GHz before the de-embedding procedure and 25 GHz after the de-embedding procedure.

cond-mat.mes-hall↗

arXiv2014

MoS2 Transistors Operating at Gigahertz Frequencies

The presence of a direct band gap and an ultrathin form factor has caused a considerable interest in two-dimensional (2D) semiconductors from the transition metal dichalcogenides (TMD) family with molybdenum disulphide (MoS2) being the most studied representative of this family of materials. While diverse electronic elements, logic circuits and optoelectronic devices have been demonstrated using ultrathin MoS2, very little is known about their performance at high frequencies where commercial devices are expected to function. Here, we report on top-gated MoS2 transistors operating in the gigahertz range of frequencies. Our devices show cutoff frequencies reaching 6 GHz. The presence of a band gap also gives rise to current saturation, allowing power and voltage gain, all in the gigahertz range. This shows that MoS2 could be an interesting material for realizing high-speed amplifiers and logic circuits with device scaling expected to result in further improvement of performance. Our work represents the first step in the realization of high-frequency analog and digital circuits based on two-dimensional semiconductors.

cond-mat.mes-hall↗

arXiv2007

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit

We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down to the transistor level, as well as to achieve a power consumption as low as 5mW/Gbit/s. Statistical simulation is used to estimate the achievable bit error rate in presence of phase and frequency errors and to prove the feasibility of the concept. VHDL modeling provides extensive verification of the topology. Thermal noise modeling based on well-known concepts delivers design parameters for the device sizing and biasing. We present two practical examples of possible design improvements analyzed and implemented with this methodology.

cs.AR↗