Yves Louet | Searcharxiv

arXiv2023

Deep Learning Aided Beamforming for Downlink Non-Orthogonal Multiple Access Systems

In this work, we investigate the optimal beamformer design for the downlink of Multiple-Input Single-Output (MISO) Non-Orthogonal Multiple Access (NOMA), mainly focusing on a two-user scenario. We derive novel closed-form expressions for the Bit Error Rate (BER) experienced by both users when Quadrature Amplitude Modulation (QAM) is employed. Using these expressions, we formulate a fairness-based optimal beamforming problem aiming to minimize the maximum BER encountered by the users. Due to the complexity of this problem and the time-consuming nature of Constraint Optimization (CO) algorithms for real-time telecommunication systems, we propose a deep learning (DL) approach for its solution. The proposed DL architecture possesses specific input and output characteristics that enable the simultaneous training and use of the system by multiple different antenna schemes. By conducting extensive simulations, we demonstrate that our proposed approach outperforms existing beamforming solutions and achieves BER performance close to that given by CO algorithms while significantly reducing the computational time needed. Finally, we conduct simulations to examine the robustness and efficiency of our system in different test scenarios.

eess.SP↗

arXiv2017

Accurate Measurement of Power Consumption Overhead During FPGA Dynamic Partial Reconfiguration

In the context of embedded systems design, two important challenges are still under investigation. First, improve real-time data processing, reconfigurability, scalability, and self-adjusting capabilities of hardware components. Second, reduce power consumption through low-power design techniques as clock gating, logic gating, and dynamic partial reconfiguration (DPR) capabilities. Today, several application, e.g., cryptography, Software-defined radio or aerospace missions exploit the benefits of DPR of programmable logic devices. The DPR allows well defined reconfigurable FPGA region to be modified during runtime. However, it introduces an overhead in term of power consumption and time during the reconfiguration phase. In this paper, we present an investigation of power consumption overhead of the DPR process using a high-speed digital oscilloscope and the shunt resistor method. Results in terms of reconfiguration time and power consumption overhead for Virtex 5 FPGAs are shown.

cs.AR↗