arXiv subjects

Zhaoran Rena Huang

Publications and source records attributed to Zhaoran Rena Huang.

6 recordsLinked to original sources

arXiv2026

A Cryogenic Hybrid Photonic/CMOS Controller Architecture for Scalable Superconducting Qubit Control

Scaling superconducting quantum computers toward thousands of control channels remains a difficult hardware problem. This requires reducing room-temperature-to-cryogenic interconnects and 4 K power while retaining channel-specific programmability. We develop a hybrid photonic/CMOS control architecture in which optical fibers distribute shared Gaussian and derivative pulse templates, while local cryogenic CMOS circuits provide event-rate amplitude programming, pulse blocking, hold-duration control, photodetection, and microwave upconversion. The architecture supports template-based XY/DRAG control and smooth-edged flat-top envelopes for two-qubit control through separate local signal paths. Compared with full-waveform Cryo-CMOS, it moves high-speed sampled-waveform generation out of each cryogenic channel. Compared with per-channel photonic waveform delivery, it retains a programmable endpoint after optical distribution for applying updated channel coefficients and control states. We evaluate the architecture using post-layout circuit simulations, optical and interconnect models, and system-level power scaling under a common 4 K output boundary. The modeled downlink power is below 1 mW per qubit-control channel at the thousand-channel scale, substantially below the normalized full-waveform Cryo-CMOS result and in the same range as the strict 50-ohm direct-detection WDM reference. Simulated I- and Q-path outputs are propagated through a five-level transmon model, while the simulated sample-and-hold output is evaluated in a coupled-transmon model. The tested single-qubit cases remain below the 10^-3 worst-state error reference, and the representative two-qubit result remains near the same scale after model-level calibration. These results support low-power photonic delivery with limited in-fridge programmability for template-compatible superconducting-qubit control.

quant-ph↗

arXiv2026

SKYLIGHT: A Scalable Hundred-Channel 3D Photonic In-Memory Tensor Core Architecture for Real-time AI Inference

The growing computational demands of artificial intelligence (AI) are challenging conventional electronics, making photonic computing a promising alternative. However, existing photonic architectures face fundamental scalability and reliability barriers. This paper introduces SKYLIGHT, a scalable 3D photonic in-memory tensor core architecture designed for real-time AI inference. By co-designing its topology, wavelength routing, accumulation, and programming in a 3D stack, SKYLIGHT overcomes key limitations. Its innovations include a low-loss 3D Si/SiN crossbar topology, a thermally robust non-micro-ring resonator (MRR)-based wavelength-division multiplexing (WDM) component, a hierarchical signal accumulation using a multi-port photodetector (PD), and optically programmed non-volatile phase-change material (PCM) weights. Importantly, SKYLIGHT enables in-situ weight updates that support label-free, layer-local learning (e.g., forward-forward local updates) in addition to inference. Using SimPhony for system-level modeling, we show that a single 144 x 256 SKYLIGHT core is feasible within a single reticle and delivers 342.1 TOPS at 23.7 TOPS/W, enabling ResNet-50 inference at 1212 FPS with 27 mJ per image, and achieves 84.17 FPS/W end-to-end (1.61 x higher than an NVIDIA RTX PRO 6000 Blackwell GPU) under the same workload in real-time measurements. System-level evaluations on four representative machine learning tasks, including unsupervised local self-learning, demonstrate SKYLIGHT's robustness to realistic hardware non-idealities (low-bit quantization and signal-proportional analog noise capturing modulation, PCM programming, and readout variations). With noise-aware training, SKYLIGHT maintains high task accuracy, validating its potential as a comprehensive solution for energy-efficient, large-scale photonic AI accelerators.

cs.ET↗

arXiv2025

Toward Large-Scale Photonics-Empowered AI Systems: From Physical Design Automation to System-Algorithm Co-Exploration

In this work, we identify three considerations that are essential for realizing practical photonic AI systems at scale: (1) dynamic tensor operation support for modern models rather than only weight-static kernels, especially for attention/Transformer-style workloads; (2) systematic management of conversion, control, and data-movement overheads, where multiplexing and dataflow must amortize electronic costs instead of letting ADC/DAC and I/O dominate; and (3) robustness under hardware non-idealities that become more severe as integration density grows. To study these coupled tradeoffs quantitatively, and to ensure they remain meaningful under real implementation constraints, we build a cross-layer toolchain that supports photonic AI design from early exploration to physical realization. SimPhony provides implementation-aware modeling and rapid cross-layer evaluation, translating physical costs into system-level metrics so architectural decisions are grounded in realistic assumptions. ADEPT and ADEPT-Z enable end-to-end circuit and topology exploration, connecting system objectives to feasible photonic fabrics under practical device and circuit constraints. Finally, Apollo and LiDAR provide scalable photonic physical design automation, turning candidate circuits into manufacturable layouts while accounting for routing, thermal, and crosstalk constraints.

physics.optics↗

arXiv2024

BOSON$^{-1}$: Understanding and Enabling Physically-Robust Photonic Inverse Design with Adaptive Variation-Aware Subspace Optimization

Nanophotonic device design aims to optimize photonic structures to meet specific requirements across various applications. Inverse design has unlocked non-intuitive, high-dimensional design spaces, enabling the discovery of high-performance devices beyond heuristic or analytic methods. The adjoint method, which calculates gradients for all variables using just two simulations, enables efficient navigation of this complex space. However, many inverse-designed structures, while numerically plausible, are difficult to fabricate and sensitive to variations, limiting their practical use. The discrete nature with numerous local-optimal structures also pose significant optimization challenges, often causing gradient-based methods to converge on suboptimal designs. In this work, we formulate inverse design as a fabrication-restricted, discrete, probabilistic optimization problem and introduce BOSON-1, an end-to-end, variation-aware subspace optimization framework to address the challenges of manufacturability, robustness, and optimizability. To overcome optimization difficulty, we propose dense target-enhanced gradient flows to mitigate misleading local optima and introduce a conditional subspace optimization strategy to create high-dimensional tunnels to escape local optima. Furthermore, we significantly reduce the runtime associated with optimizing across exponential variation samples through an adaptive sampling-based robust optimization, ensuring both efficiency and variation robustness. On three representative photonic device benchmarks, our proposed inverse design methodology BOSON^-1 delivers fabricable structures and achieves the best convergence and performance under realistic variations, outperforming prior arts with 74.3% post-fabrication performance. We open-source our codes at https://github.com/ScopeX-ASU/BOSON.

physics.optics↗

arXiv2024

Silicon Photonics Foundry Fabricated, Slow-Light Enhanced, Low Power Thermal Phase Shifter

In this research, we developed a low-power silicon photonics foundry-fabricated slow-light thermal phase shifter (SLTPS) where the slow-light (SL) effect is achieved using an integrated Bragg grating (BG) waveguide. Heating the grating induces a red shift in the transmission spectrum, leading to an increased group index $n_g$ during operation, which facilitates a further reduction in the voltage needed for a $π$ phase shift, i.e. $V_π$. Additionally, we investigated a compact Mach-Zehnder Interferometer (MZI) that incorporates the SLTPS in both arms with a phase shifter length of 50 $μ$m. A detailed theoretical analysis was conducted to address the non-idealities of the SL-MZI due to uneven optical power splitting and unbalanced loss in the two MZI arms. The $V_π$ and power consumption for a $π$ phase shift $(P_π)$ of the SL-MZI were quantified for operation in the slow light regime, demonstrating a $V_π$ of 1.1 V and a $P_π$ of 3.63 mW at an operational wavelength near the photonic band edge. The figure of merit (FOM) $P_π \times τ$ is commonly used to assess the performance of thermal optical switches. The SL-MZI in this work has achieved a low $P_π \times τ$ of 5.1 mW $μ$s. Insertion loss of the SL-MZI ranges from 1.3 dB to 4.4 dB depending on the operation wavelength, indicating a trade-off with the $V_π$ reduction.

physics.optics↗

arXiv2024

TeMPO: Efficient Time-Multiplexed Dynamic Photonic Tensor Core for Edge AI with Compact Slow-Light Electro-Optic Modulator

Electronic-photonic computing systems offer immense potential in energy-efficient artificial intelligence (AI) acceleration tasks due to the superior computing speed and efficiency of optics, especially for real-time, low-energy deep neural network (DNN) inference tasks on resource-restricted edge platforms. However, current optical neural accelerators based on foundry-available devices and conventional system architecture still encounter a performance gap compared to highly customized electronic counterparts. To bridge the performance gap due to lack of domain specialization, we present a time-multiplexed dynamic photonic tensor accelerator, dubbed TeMPO, with cross-layer device/circuit/architecture customization. At the device level, we present foundry-compatible, customized photonic devices, including a slow-light electro-optic modulator with experimental demonstration, optical splitters, and phase shifters that significantly reduce the footprint and power in input encoding and dot-product calculation. At the circuit level, partial products are hierarchically accumulated via parallel photocurrent aggregation, lightweight capacitive temporal integration, and sequential digital summation, considerably relieving the analog-to-digital conversion bottleneck. We also employ a multi-tile, multi-core architecture to maximize hardware sharing for higher efficiency. Across diverse edge AI workloads, TeMPO delivers digital-comparable task accuracy with superior quantization/noise tolerance. We achieve a 368.6 TOPS peak performance, 22.3 TOPS/W energy efficiency, and 1.2 TOPS/mm$^2$ compute density, pushing the Pareto frontier in edge AI hardware. This work signifies the power of cross-layer co-design and domain-specific customization, paving the way for future electronic-photonic accelerators with even greater performance and efficiency.

cs.ET↗