Zhenghan Li | Searcharxiv

arXiv2026

Tree-aggregated compositional regression under measurement error

Compositional covariates in microbiome studies are often measured with error and organized by a biological hierarchy. Tree aggregation can improve multiresolution interpretation, but it also combines leaf-level errors into correlated contamination whose scale varies across the hierarchy. Existing tree aggregation and compositional measurement-error correction do not combine directly in redundant tree coordinates because a generic positive semidefinite projection can make the corrected criterion depend on the chosen representation. TARCO resolves this mismatch by normalizing tree coordinates by descendant leaf counts and applying a kernel-preserving positive semidefinite projection to the corrected tree-space Gram matrix. The resulting criterion is constant across equivalent tree representations, and the tree-coordinate estimator is exactly equivalent to an estimator on the identifiable coefficient space. For this estimator, we establish finite-sample prediction and coefficient-estimation bounds and, under sufficient separation and an appropriate grouping threshold, exact recovery of the maximal constant subtrees of the identifiable coefficient. These guarantees extend, with additional covariance-estimation terms, when the measurement-error covariance is estimated from independent auxiliary technical replicates. In a longitudinal gut microbiome analysis, correction changes the displayed taxonomic resolution of some associations with body mass index while preserving their directions, illustrating why the hierarchy should guide both signal aggregation and error correction.

stat.ME↗

arXiv2025

Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead

Code generation has emerged as a critical research area at the intersection of Software Engineering (SE) and Artificial Intelligence (AI), attracting significant attention from both academia and industry. Within this broader landscape, Verilog, as a representative hardware description language (HDL), plays a fundamental role in digital circuit design and verification, making its automated generation particularly significant for Electronic Design Automation (EDA). Consequently, recent research has increasingly focused on applying Large Language Models (LLMs) to Verilog code generation, particularly at the Register Transfer Level (RTL), exploring how these AI-driven techniques can be effectively integrated into hardware design workflows. Despite substantial research efforts have explored LLM applications in this domain, a comprehensive survey synthesizing these developments remains absent from the literature. This review fill addresses this gap by providing a systematic literature review of LLM-based methods for Verilog code generation, examining their effectiveness, limitations, and potential for advancing automated hardware design. The review encompasses research work from conferences and journals in the fields of SE, AI, and EDA, encompassing 70 papers published on venues, along with 32 high-quality preprint papers, bringing the total to 102 papers. By answering four key research questions, we aim to (1) identify the LLMs used for Verilog generation, (2) examine the datasets and metrics employed in evaluation, (3) categorize the techniques proposed for Verilog generation, and (4) analyze LLM alignment approaches for Verilog generation. Based on our findings, we have identified a series of limitations of existing studies. Finally, we have outlined a roadmap highlighting potential opportunities for future research endeavors in LLM-assisted hardware design.

cs.AR↗