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Zhengya Zhang

Publications and source records attributed to Zhengya Zhang.

11 recordsLinked to original sources

A Linear Structure from Magnetic-Dipole Systems and Its Geometry

We investigate a class of algebras on $\mathbb{R}^3$ arising and generalized from the algebraic structure of magnetic gradient fields induced by systems of synchronous magnets with identical dipole moments (i.e., $\mathbf{M}_i=\mathbf{M},\,\forall i$). We show that when there is a $2$ dimensional sub-algebra, the linear structure associated to such an algebra admits a certain type of decompositions, which allows the locating of the dipole moment $\bar{\mathbf{M}}$ that yields the strongest translational force(s) on a test magnet $\mathfrak{m}$. Upper bounds to the strength of this magnetic force are then established.

math.RA

Tiled Beamspace MVDR for 1024-element Wideband Radar

We present a tiled architecture for computationally efficient digital beamforming for wideband massive MIMO radar, using beamspace dimension reduction for each tile, and coordinated training of reduced-dimension MVDR beamformers across tiles. We illustrate the efficacy of our approach for a setting in which a 1024-element airborne radar platform beamforms towards airborne targets while suppressing strong interference from ground transmitters. The array is organized into eight 128-element tiles, each a 2D array with 4 (vertical) x 32 (horizontal) elements. Each tile applies a 2D spatial DFT to achieve energy concentration in beamspace, and a 1D temporal FFT to channelize the wideband signal into subbands for which narrowband array models apply. A small tile-level beamspace window is selected for each target (depending on its angle of arrival) in each subband, and coordinated training across tiles is used to compute reduced-dimension MVDR beamformers per-target, per-subband. While full-dimensional MVDR processing is infeasible for the system under consideration, we show that our proposed approach significantly outperforms beamspace MVDR beamforming for a single 128-element tile, where we set the dimensions of the spatial filter (and hence the complexity of MVDR training) to be equal in both systems.

eess.SP

Scaling Wideband Massive MIMO Radar via Beamspace Dimension Reduction

We present an architecture for scaling digital beamforming for wideband massive MIMO radar. Conventional spatial processing becomes computationally prohibitive as array size grows; for example, the computational complexity of MVDR beamforming scales as O(N^3) for an N-element array. In this paper, we show that energy concentration in beamspace provides the basis for drastic complexity reduction, with array scaling governed by the O(NlogN) complexity of the spatial FFT used for beamspace transformation. Specifically, we propose an architecture for windowed beamspace MVDR beamforming, parallelized across targets and subbands, and evaluate its efficacy for beamforming and interference suppression for government-supplied wideband radar data from the DARPA SOAP (Scalable On-Array Processing) program. We demonstrate that our approach achieves detection performance comparable to full-dimensional benchmarks while significantly reducing computational and training overhead, and provide insight into tradeoffs between beamspace window size and FFT resolution in balancing complexity, detection accuracy, and interference suppression.

eess.SP

Adaptive Attention-Based Model for 5G Radio-based Outdoor Localization

Radio-based localization in dynamic environments, such as urban and vehicular settings, requires systems that efficiently adapt to varying signal conditions and environmental changes. Factors like multipath interference and obstructions introduce different levels of complexity that affect the accuracy of the localization. Although generalized models offer broad applicability, they often struggle to capture the nuances of specific environments, leading to suboptimal performance in real-world deployments. In contrast, specialized models can be tailored to particular conditions, enabling more precise localization by effectively handling domain-specific variations, which also results in reduced execution time and smaller model size. However, deploying multiple specialized models requires an efficient mechanism to select the most appropriate one for a given scenario. In this work, we develop an adaptive localization framework that combines shallow attention-based models with a router/switching mechanism based on a single-layer perceptron. This enables seamless transitions between specialized localization models optimized for different conditions, balancing accuracy and computational complexity. We design three low-complex models tailored for distinct scenarios, and a router that dynamically selects the most suitable model based on real-time input characteristics. The proposed framework is validated using real-world vehicle localization data collected from a massive MIMO base station and compared to more general models.

eess.SP

SteROI-D: System Design and Mapping for Stereo Depth Inference on Regions of Interest

Machine learning algorithms have enabled high quality stereo depth estimation to run on Augmented and Virtual Reality (AR/VR) devices. However, high energy consumption across the full image processing stack prevents stereo depth algorithms from running effectively on battery-limited devices. This paper introduces SteROI-D, a full stereo depth system paired with a mapping methodology. SteROI-D exploits Region-of-Interest (ROI) and temporal sparsity at the system level to save energy. SteROI-D's flexible and heterogeneous compute fabric supports diverse ROIs. Importantly, we introduce a systematic mapping methodology to effectively handle dynamic ROIs, thereby maximizing energy savings. Using these techniques, our 28nm prototype SteROI-D design achieves up to 4.35x reduction in total system energy compared to a baseline ASIC.

cs.CV

Panacea: Novel DNN Accelerator using Accuracy-Preserving Asymmetric Quantization and Energy-Saving Bit-Slice Sparsity

Low bit-precisions and their bit-slice sparsity have recently been studied to accelerate general matrix-multiplications (GEMM) during large-scale deep neural network (DNN) inferences. While the conventional symmetric quantization facilitates low-resolution processing with bit-slice sparsity for both weight and activation, its accuracy loss caused by the activation's asymmetric distributions cannot be acceptable, especially for large-scale DNNs. In efforts to mitigate this accuracy loss, recent studies have actively utilized asymmetric quantization for activations without requiring additional operations. However, the cutting-edge asymmetric quantization produces numerous nonzero slices that cannot be compressed and skipped by recent bit-slice GEMM accelerators, naturally consuming more processing energy to handle the quantized DNN models. To simultaneously achieve high accuracy and hardware efficiency for large-scale DNN inferences, this paper proposes an Asymmetrically-Quantized bit-Slice GEMM (AQS-GEMM) for the first time. In contrast to the previous bit-slice computing, which only skips operations of zero slices, the AQS-GEMM compresses frequent nonzero slices, generated by asymmetric quantization, and skips their operations. To increase the slice-level sparsity of activations, we also introduce two algorithm-hardware co-optimization methods: a zero-point manipulation and a distribution-based bit-slicing. To support the proposed AQS-GEMM and optimizations at the hardware-level, we newly introduce a DNN accelerator, Panacea, which efficiently handles sparse/dense workloads of the tiled AQS-GEMM to increase data reuse and utilization. Panacea supports a specialized dataflow and run-length encoding to maximize data reuse and minimize external memory accesses, significantly improving its hardware efficiency. Our benchmark evaluations show Panacea outperforms existing DNN accelerators.

cs.AR

HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer

Memory-augmented neural networks (MANNs) provide better inference performance in many tasks with the help of an external memory. The recently developed differentiable neural computer (DNC) is a MANN that has been shown to outperform in representing complicated data structures and learning long-term dependencies. DNC's higher performance is derived from new history-based attention mechanisms in addition to the previously used content-based attention mechanisms. History-based mechanisms require a variety of new compute primitives and state memories, which are not supported by existing neural network (NN) or MANN accelerators. We present HiMA, a tiled, history-based memory access engine with distributed memories in tiles. HiMA incorporates a multi-mode network-on-chip (NoC) to reduce the communication latency and improve scalability. An optimal submatrix-wise memory partition strategy is applied to reduce the amount of NoC traffic; and a two-stage usage sort method leverages distributed tiles to improve computation speed. To make HiMA fundamentally scalable, we create a distributed version of DNC called DNC-D to allow almost all memory operations to be applied to local memories with trainable weighted summation to produce the global memory output. Two approximation techniques, usage skimming and softmax approximation, are proposed to further enhance hardware efficiency. HiMA prototypes are created in RTL and synthesized in a 40nm technology. By simulations, HiMA running DNC and DNC-D demonstrates 6.47x and 39.1x higher speed, 22.8x and 164.3x better area efficiency, and 6.1x and 61.2x better energy efficiency over the state-of-the-art MANN accelerator. Compared to an Nvidia 3080Ti GPU, HiMA demonstrates speedup by up to 437x and 2,646x when running DNC and DNC-D, respectively.

cs.AR

Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes

The error floor phenomenon, associated with iterative decoders, is one of the most significant limitations to the applications of low-density parity-check (LDPC) codes. A variety of techniques from code design to decoder implementation have been proposed to address the error floor problem, among which post-processors have shown to be both effective and implementation-friendly. In this work, we take the inspiration from simulated annealing to generalize the post-processor design using three methods: quenching, extended heating, and focused heating, each of which targets a different error structure. The resulting post-processor is demonstrated to lower the error floors by two orders of magnitude for two structured code examples, a (2209, 1978) array LDPC code, and a (1944, 1620) LDPC code used by the IEEE 802.11n standard. The post-processor can be integrated to a belief-propagation decoder with minimal overhead. The post-processor design is equally applicable to other structured LDPC codes.

cs.IT

DNC-Aided SCL-Flip Decoding of Polar Codes

Successive-cancellation list (SCL) decoding of polar codes has been adopted for 5G. However, the performance is not very satisfactory with moderate code length. Heuristic or deep-learning-aided (DL-aided) flip algorithms have been developed to tackle this problem. The key for successful flip decoding is to accurately identify error bit positions. In this work, we propose a new flip algorithm with help of differentiable neural computer (DNC). New state and action encoding are developed for better DNC training and inference efficiency. The proposed method consists of two phases: i) a flip DNC (F-DNC) is exploited to rank most likely flip positions for multi-bit flipping; ii) if decoding still fails, a flip-validate DNC (FV-DNC) is used to re-select error bit positions for successive flip decoding trials. Supervised training methods are designed accordingly for the two DNCs. Simulation results show that proposed DNC-aided SCL-Flip (DNC-SCLF) decoding demonstrates up to 0.34dB coding gain improvement or 54.2 reduction in average number of decoding attempts compared to prior works.

cs.IT

Field-Programmable Crossbar Array (FPCA) for Reconfigurable Computing

For decades, advances in electronics were directly driven by the scaling of CMOS transistors according to Moore's law. However, both the CMOS scaling and the classical computer architecture are approaching fundamental and practical limits, and new computing architectures based on emerging devices, such as resistive random-access memory (RRAM) devices, are expected to sustain the exponential growth of computing capability. Here we propose a novel memory-centric, reconfigurable, general purpose computing platform that is capable of handling the explosive amount of data in a fast and energy-efficient manner. The proposed computing architecture is based on a uniform, physical, resistive, memory-centric fabric that can be optimally reconfigured and utilized to perform different computing and data storage tasks in a massively parallel approach. The system can be tailored to achieve maximal energy efficiency based on the data flow by dynamically allocating the basic computing fabric for storage, arithmetic, and analog computing including neuromorphic computing tasks.

cs.ET

Absorbing Set Spectrum Approach for Practical Code Design

This paper focuses on controlling the absorbing set spectrum for a class of regular LDPC codes known as separable, circulant-based (SCB) codes. For a specified circulant matrix, SCB codes all share a common mother matrix, examples of which are array-based LDPC codes and many common quasi-cyclic codes. SCB codes retain the standard properties of quasi-cyclic LDPC codes such as girth, code structure, and compatibility with efficient decoder implementations. In this paper, we define a cycle consistency matrix (CCM) for each absorbing set of interest in an SCB LDPC code. For an absorbing set to be present in an SCB LDPC code, the associated CCM must not be full columnrank. Our approach selects rows and columns from the SCB mother matrix to systematically eliminate dominant absorbing sets by forcing the associated CCMs to be full column-rank. We use the CCM approach to select rows from the SCB mother matrix to design SCB codes of column weight 5 that avoid all low-weight absorbing sets (4, 8), (5, 9), and (6, 8). Simulation results demonstrate that the newly designed code has a steeper error-floor slope and provides at least one order of magnitude of improvement in the low error rate region as compared to an elementary array-based code.

cs.IT