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Zhilei Chai

Publications and source records attributed to Zhilei Chai.

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L-PCN: A Point Cloud Accelerator Exploiting Spatial Locality through Octree-based Islandization

Existing Point Cloud Networks (PCNs) have proven to achieve great success in many point cloud tasks such as object part segmentation, shape classification, and so on. The most popular point-based PCNs are usually composed of two sequential steps: Data Structuring (DS) and Feature Computation (FC). In this paper, we first describe an important characteristic of the PCN-specific DS step that has not been addressed in existing PCN accelerators: the spatial locality resulting from overlapping points of the gathered point subsets. Using algorithm-hardware co-design, L-PCN (Locality-aware PCN) proposes two novel techniques to exploit this characteristic to reduce the large amount of repetitive operations in the overall PCN. The first of which is a point cloud partitioning technique, Octree-based Islandization. Using Octree-based adjacency gathering, a point cloud is partitioned into islands in L-PCN, where the point subsets inside the same island exhibit a strong spatial correlation. After partitioning, L-PCN performs the rest of PCN steps at the granularity of islands. The second method of L-PCN is scheduling the intra-island computation with a Hub-based Scheduling to exploit the intra-island data reuse by dynamically caching, updating, and reusing the repeated data. The two methods are implemented in an Islandization Unit, which can be seamlessly integrated into standard PCN workflow. Our evaluation shows that based on our methods for exploiting spatial locality, L-PCN achieves a theoretical reduction in feature fetching ranging from 55.2% to 93.8% and in feature computation ranging from 45.4% to 80.6% during the PCN process. For experimentation, prototype L-PCN accelerators are implemented on the Intel Arria 10 GX FPGA. Experimental results prove that with the Islandization Unit as a plug-in, state-of-the-art PCN accelerators can achieve an additional speedup ranging from 1.2x to 3.2x.

cs.AR

OpenHEC: A Framework for Application Programmers to Design FPGA-based Systems

Today, there is a trend to incorporate more intelligence (e.g., vision capabilities) into a wide range of devices, which makes high performance a necessity for computing systems. Furthermore, for embedded systems, low power consumption should be generally considered together with high computing performance. FPGAs, as programmable logic devices able to support different types of fine-grained parallelisms, their power and performance advantages were recognized widely. However, designing applications on FPGA-based systems is traditionally far from a task can be carried out by software programmers. Generally, hardware engineers and even system-level software engineers have more hardware/architectural knowledge but fewer algorithm and application knowledge. Thus, it is critical for computing systems to allow application-level programmers to realize their idea conveniently, which is popular in computing systems based on the general processor. In this paper, the OpenHEC (Open Framework for High-Efficiency Computing) framework is proposed to provide a design framework for application-level software programmers to use FPGA-based platforms. It frees users from hardware and architectural details to let them focus more on algorithms/applications. This framework was integrated with the commercial Xilinx ISE/Vivado to make it to be used immediately. After implementing a widely-used feature detection algorithm on OpenHEC from the perspective of software programmers, it shows this framework is applicable for application programmers with little hardware knowledge.

cs.OH