arXiv subjects

Zhongfeng Wang

Publications and source records attributed to Zhongfeng Wang.

57 records · Page 4Linked to original sources

arXiv2016

Intra-layer Nonuniform Quantization for Deep Convolutional Neural Network

Deep convolutional neural network (DCNN) has achieved remarkable performance on object detection and speech recognition in recent years. However, the excellent performance of a DCNN incurs high computational complexity and large memory requirement. In this paper, an equal distance nonuniform quantization (ENQ) scheme and a K-means clustering nonuniform quantization (KNQ) scheme are proposed to reduce the required memory storage when low complexity hardware or software implementations are considered. For the VGG-16 and the AlexNet, the proposed nonuniform quantization schemes reduce the number of required memory storage by approximately 50\% while achieving almost the same or even better classification accuracy compared to the state-of-the-art quantization method. Compared to the ENQ scheme, the proposed KNQ scheme provides a better tradeoff when higher accuracy is required.

cs.CV↗

arXiv2012

Super-FEC Codes for 40/100 Gbps Networking

This paper presents a simple approach to evaluate the performance bound at very low bit-error-rate (BER) range for binary pseudo-product codes and true-product codes. Moreover it introduces a super-product BCH code that can achieve near-Shannon limit performance with very low decoding complexity. This work has been accepted by IEEE Communications Letters for future publication. Copyright may be transferred without notice, after which this version may no longer be accessible.

cs.IT↗

arXiv2012

Reduced-Complexity Column-Layered Decoding and Implementation for LDPC Codes

Layered decoding is well appreciated in Low-Density Parity-Check (LDPC) decoder implementation since it can achieve effectively high decoding throughput with low computation complexity. This work, for the first time, addresses low complexity column-layered decoding schemes and VLSI architectures for multi-Gb/s applications. At first, the Min-Sum algorithm is incorporated into the column-layered decoding. Then algorithmic transformations and judicious approximations are explored to minimize the overall computation complexity. Compared to the original column-layered decoding, the new approach can reduce the computation complexity in check node processing for high-rate LDPC codes by up to 90% while maintaining the fast convergence speed of layered decoding. Furthermore, a relaxed pipelining scheme is presented to enable very high clock speed for VLSI implementation. Equipped with these new techniques, an efficient decoder architecture for quasi-cyclic LDPC codes is developed and implemented with 0.13um CMOS technology. It is shown that a decoding throughput of nearly 4 Gb/s at maximum of 10 iterations can be achieved for a (4096, 3584) LDPC code. Hence, this work has facilitated practical applications of column-layered decoding and particularly made it very attractive in high-speed, high-rate LDPC decoder implementation.

cs.IT↗