arXiv subjects

Ziheng Zheng

Publications and source records attributed to Ziheng Zheng.

3 recordsLinked to original sources

arXiv2026

Extended Proofs for Encrypted Sensing in Bistatic Radar: Unified Analysis and Randomly Activated Arrays

This supplementary material provides the complete mathematical development for the signal-to-noise ratio loss (SNRL) analysis of pulse-wise spatially randomized encrypted sensing. We first derive a reduced model in which the transmit-side randomization is represented by an independent and identically distributed complex spatial coefficient. Based on this model, we establish the almost-sure and mean asymptotic SNRL, derive the leading bias and variance for a finite coherent processing interval (CPI), and obtain closed-form coefficient moments and asymptotic SNRL for independent Bernoulli element activation. These results complement the concise statements and proof sketches in the associated paper.

eess.SP↗

arXiv2022

Towards a performance bound on MIMO DFRC systems

It is a fundamental problem to analyse the performance bound of multiple-input multiple-output (MIMO) dual-functional radar-communication (DFRC) systems. To this end, we derive a performance bound on the communication function under a constraint on radar performance. To facilitate the analysis, we consider a toy example, in which there is only one down-link user with a single receive antenna and one radar target. In such a simplified case, we obtain an analytical expression for the performance bound and the corresponding waveform design strategy to achieve the bound. The results reveal a tradeoff between communication and radar performance, and a condition when the transmitted energy can be shared between these two functions.

cs.IT↗

arXiv2022

ALL-MASK: A Reconfigurable Logic Locking Method for Multicore Architecture with Sequential-Instruction-Oriented Key

Intellectual property (IP) piracy has become a non-negligible problem as the integrated circuit (IC) production supply chain is becoming increasingly globalized and separated that enables attacks by potentially untrusted attackers. Logic locking is a widely adopted method to lock the circuit module with a key and prevent hackers from cracking it. The key is the critical aspect of logic locking, but the existing works have overlooked three possible challenges of the key: safety of key storage, easy key-attempt from interface and key-related overheads, bringing the further challenges of low error rate and small state space. In this work, the key is dynamically generated by utilizing the huge space of a CPU core, and the unlocking is performed implicitly through the interconnection inside the chip. A novel low-cost logic reconfigurable gate is together proposed with ferroelectric FET (FeFET) to mitigate the reverse engineering and removal attack. Compared to the common logic locking methods, our proposed approach is 19,945 times more time consuming to traverse all the possible combinations in only 9-bit-key condition. Furthermore, our technique let key length increases this complexity exponentially and ensure the logic obfuscation effect.

cs.AR↗