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Zonghui Li

Publications and source records attributed to Zonghui Li.

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Anchoring on Reality: Breaking the Pseudo-Target Ceiling in Makeup Transfer

Makeup transfer applies a reference cosmetic style to a source face while preserving its identity and geometry. However, this task is severely hindered by the lack of real paired training data. Current methods rely on either weak priors or synthetic pseudo-targets from large-scale editing models. These paradigms provide suboptimal guidance, often leading to degraded fine-grained details, synthetic artifacts, and identity drift. To this end, we propose Anchoring on Reality Makeup Transfer (ART), a two-stage framework with a reality-anchored refinement cycle. In Stage I, the model is initialized with pseudo-targets to establish basic semantic alignment and global makeup placement. Crucially, Stage II shifts supervision from pseudo-targets to the real reference, reconstructing it from its bare-skin counterpart through a differentiable cycle that penalizes any omitted detail and overrides synthetic artifacts. Furthermore, we introduce MakeupFaces2K (MF2K), the first 2K-resolution in-the-wild makeup portrait dataset comprising 8,573 images. Extensive experiments demonstrate that our method achieves superior makeup fidelity, strong background stability, and robust identity preservation, especially for complex makeup styles.

cs.CV

SSR-Merge: Subspace Signal Routing for Training-Free LoRA Merging in Diffusion Models

Low-Rank Adaptation (LoRA) merging can efficiently combine diverse generative capabilities from multiple trained LoRAs for a diffusion model. However, existing LoRA merging techniques often suffer from severe parameter interference, causing destructive collisions in the shared parameter space. To address this, we propose Subspace Signal Routing (SSR), which resolves interference by routing internal signals instead of performing parameter-space merge. Specifically, SSR first constructs a unified subspace by concatenating candidate LoRAs along the rank dimension. Next, SSR employs an inverse correlation matrix to decorrelate mixed signals within this space. Finally, a directional guide matrix steers these purified signals into their respective task-specific subspaces. We provide a rigorous theoretical analysis proving that SSR aligns with the Ordinary Least Squares (OLS) solution, thereby ensuring mathematical optimality. We utilize the additivity of sufficient statistics to design a streaming algorithm. This enables on-the-fly updates that significantly reduce memory overhead and computation time. Extensive experiments validate that SSR significantly outperforms state-of-the-art methods while maintaining comparable efficiency. Code is available at https://github.com/nagara214/SSR-Merge.

cs.CV

CRT: Collision-Tolerant Residence Time for Deterministic Transmission in LEO Satellite Networks

Low-Earth Orbit (LEO) satellite networks are a key enabler for the 6G Non-Terrestrial Network (NTN) architecture. However, supporting time-sensitive services in LEO networks is challenging due to highly dynamic topologies and the difficulty of maintaining precise global time synchronization. Existing Time-Sensitive Networking (TSN) mechanisms largely rely on static topologies and strict synchronization, which makes them ill-suited to dynamic LEO environments. To address this issue, we propose CRT, a deterministic transmission framework tailored for LEO networks. CRT regulates per-hop residence time using local clocks, thereby compensating for link-delay variations without requiring strict global synchronization. To handle asynchronous collisions, CRT adopts a collision-tolerant scheduling strategy that maximizes the number of schedulable flows while bounding collision-induced jitter. We formalize the corresponding scheduling problem and show that it is NP-hard. We further develop CRT-Fast, an efficient heuristic algorithm. It combines iterative layering with path continuity to control collision intensity and improve path stability under topology changes. Simulations on Iridium and Starlink constellations show that the proposed method achieves lower delay jitter and high schedulability under heavy traffic loads.

cs.NI

KRIS-Bench: Benchmarking Next-Level Intelligent Image Editing Models

Recent advances in multi-modal generative models have enabled significant progress in instruction-based image editing. However, while these models produce visually plausible outputs, their capacity for knowledge-based reasoning editing tasks remains under-explored. In this paper, we introduce KRIS-Bench (Knowledge-based Reasoning in Image-editing Systems Benchmark), a diagnostic benchmark designed to assess models through a cognitively informed lens. Drawing from educational theory, KRIS-Bench categorizes editing tasks across three foundational knowledge types: Factual, Conceptual, and Procedural. Based on this taxonomy, we design 22 representative tasks spanning 7 reasoning dimensions and release 1,267 high-quality annotated editing instances. To support fine-grained evaluation, we propose a comprehensive protocol that incorporates a novel Knowledge Plausibility metric, enhanced by knowledge hints and calibrated through human studies. Empirical results on 10 state-of-the-art models reveal significant gaps in reasoning performance, highlighting the need for knowledge-centric benchmarks to advance the development of intelligent image editing systems.

cs.CV

Delay Performance Analysis of Delay-Deterministic Wireless Networks with Infinite and Finite Blocklength Transmission

In order to achieve stable and reliable industrial manufacturing, wireless networks must meet the stringent communication requirements of industrial automation, particularly the need for deterministic low latency communication. The limited wireless resources and time-varying fading channel contribute to the random fluctuations of transmission delay, making it challenging to realize delay-deterministic wireless networks. An open challenge in this context is to model delay determinism, also known as jitter, and analyze delay performance. In this paper, we model jitter as the variance of delay and conduct a comprehensive analysis of delay performance. Specifically, we consider two transmission regimes: infinite blocklength (IBL) and finite blocklength (FBL). In the IBL regime, the distribution of the transmission delay is analyzed, and the closed-form expressions for the average delay, jitter, and delay violation probability are derived. In the FBL regime, an upper bound on the transmission delay is first approximated at a high signalto-noise ratio. Based on this upper bound, the delay distribution, delay violation probability, average delay, and jitter are derived. Finally, simulation results are provided to validate the accuracy of the analysis and derivations. Additionally, the impact of system parameters on jitter is analyzed to gain further insights.

math.OC

Time Synchronization for 5G and TSN Integrated Networking

Emerging industrial applications involving robotic collaborative operations and mobile robots require a more reliable and precise wireless network for deterministic data transmission. To meet this demand, the 3rd Generation Partnership Project (3GPP) is promoting the integration of 5th Generation Mobile Communication Technology (5G) and Time-Sensitive Networking (TSN). Time synchronization is essential for deterministic data transmission. Based on the 3GPP's vision of the 5G and TSN integrated networking with interoperability, we improve the time synchronization of TSN to conquer the multi-gNB competition, re-transmission, and mobility problems for the integrated 5G time synchronization. We implemented the improvement mechanisms and systematically validated the performance of 5G+TSN time synchronization. Based on the simulation in 500m x 500m industrial environments, the improved time synchronization achieved a precision of 1 microsecond with interoperability between 5G nodes and TSN nodes.

cs.NI

End-to-End Asynchronous Traffic Scheduling in Converged 5G and Time-Sensitive Networks

As required by Industry 4.0, companies will move towards flexible and individual manufacturing. To succeed in this transition, convergence of 5G and time-sensitive networks (TSN) is the most promising technology and has thus attracted considerable interest from industry and standardization groups. However, the delay and jitter of end-to-end (e2e) transmission will get exacerbated if the transmission opportunities are missed in TSN due to the 5G transmission jitter and the clock skew between the two network systems. To mitigate this phenomenon, we propose a novel asynchronous access mechanism (AAM) that isolates the jitter only in the 5G system and ensures zero transmission jitter in TSN. We then exploit AAM to develop an e2e asynchronous traffic scheduling model for coordinated allocation of resources for 5G and TSN to provide e2e transmission delay guarantees for time-critical flows. The results of our extensive simulation of AAM on OMNET++ corroborate the superior performance of AAM and the scheduling model.

cs.NI

A Switch Architecture for Time-Triggered Transmission with Best-Effort Delivery

In Time-Triggered (TT) or time-sensitive networks, the transmission of a TT frame is required to be scheduled at a precise time instant for industrial distributed real-time control systems. Other (or {\em best-effort} (BE)) frames are forwarded in a BE manner. Under this scheduling strategy, the transmission of a TT frame must wait until its scheduled instant even if it could have been transmitted sooner. On the other hand, BE frames are transmitted whenever possible but may miss deadlines or may even be dropped due to congestion. As a result, TT transmission and BE delivery are incompatible with each other. To remedy this incompatibility, we propose a synergistic switch architecture (SWA) for TT transmission with BE delivery to dynamically improve the end-to-end (e2e) latency of TT frames by opportunistically exploiting BE delivery. Given a TT frame, the SWA generates and transmits a cloned copy with BE delivery. The first frame arriving at the receiver device is delivered with a configured jitter and the other copy ignored. So, the SWA achieves shorter latency and controllable jitter, the best of both worlds. We have implemented SWA using FPGAs in an industry-strength TT switches and used four test scenarios to demonstrate SWA's improvements of e2e latency and controllable jitter over the state-of-the-art TT transmission scheme.

cs.NI