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At least 37 records · Page 2Linked to original sources

arXiv2007

HEBS: Histogram Equalization for Backlight Scaling

In this paper, a method is proposed for finding a pixel transformation function that maximizes backlight dimming while maintaining a pre-specified image distortion level for a liquid crystal display. This is achieved by finding a pixel transformation function, which maps the original image histogram to a new histogram with lower dynamic range. Next the contrast of the transformed image is enhanced so as to compensate for brightness loss that would arise from backlight dimming. The proposed approach relies on an accurate definition of the image distortion which takes into account both the pixel value differences and a model of the human visual system and is amenable to highly efficient hardware realization. Experimental results show that the histogram equalization for backlight scaling method results in about 45% power saving with an effective distortion rate of 5% and 65% power saving for a 20% distortion rate. This is significantly higher power savings compared to previously reported backlight dimming approaches.

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arXiv2007

Noise Figure Evaluation Using Low Cost BIST

A technique for evaluating noise figure suitable for BIST implementation is described. It is based on a low cost single-bit digitizer, which allows the simultaneous evaluation of noise figure in several test points of the analog circuit. The method is also able to benefit from SoC resources, like memory and processing power. Theoretical background and experimental results are presented in order to demonstrate the feasibility of the approach.

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arXiv2007

Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling

This paper presents new fast exact feasibility tests for uniprocessor real-time systems using preemptive EDF scheduling. Task sets which are accepted by previously described sufficient tests will be evaluated in nearly the same time as with the old tests by the new algorithms. Many task sets are not accepted by the earlier tests despite them beeing feasible. These task sets will be evaluated by the new algorithms a lot faster than with known exact feasibility tests. Therefore it is possible to use them for many applications for which only sufficient test are suitable. Additionally this paper shows that the best previous known sufficient test, the best known feasibility bound and the best known approximation algorithm can be derived from these new tests. In result this leads to an integrated schedulability theory for EDF.

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arXiv2007

Q-DPM: An Efficient Model-Free Dynamic Power Management Technique

When applying Dynamic Power Management (DPM) technique to pervasively deployed embedded systems, the technique needs to be very efficient so that it is feasible to implement the technique on low end processor and tight-budget memory. Furthermore, it should have the capability to track time varying behavior rapidly because the time varying is an inherent characteristic of real world system. Existing methods, which are usually model-based, may not satisfy the aforementioned requirements. In this paper, we propose a model-free DPM technique based on Q-Learning. Q-DPM is much more efficient because it removes the overhead of parameter estimator and mode-switch controller. Furthermore, its policy optimization is performed via consecutive online trialing, which also leads to very rapid response to time varying behavior.

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arXiv2007

A New Approach to Component Testing

Carefully tested electric/electronic components are a requirement for effective hardware-in-the-loop tests and vehicle tests in automotive industry. A new method for definition and execution of component tests is described. The most important advantage of this method is independance from the test stand. It therefore offers the oppportunity to build up knowledge over a long period of time and the ability to share this knowledge with different partners.

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arXiv2007

Embedded Automotive System Development Process

Model based design enables the automatic generation of final-build software from models for high-volume automotive embedded systems. This paper presents a framework of processes, methods and tools for the design of automotive embedded systems. A steer-by-wire system serves as an example.

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arXiv2007

An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms

In this work we consider battery powered portable systems which either have Field Programmable Gate Arrays (FPGA) or voltage and frequency scalable processors as their main processing element. An application is modeled in the form of a precedence task graph at a coarse level of granularity. We assume that for each task in the task graph several unique design-points are available which correspond to different hardware implementations for FPGAs and different voltage-frequency combinations for processors. It is assumed that performance and total power consumption estimates for each design-point are available for any given portable platfrom, including the peripheral components such as memory and display power usage. We present an iterative heuristic algorithm which finds a sequence of tasks along with an appropriate design-point for each task, such that a deadline is met and the amount of battery energy used is as small as possible. A detailed illustrative example along with a case study of a real-world application of a robotic arm controller which demonstrates the usefulness of our algorithm is also presented.

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arXiv2007

Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling

A novel energy reduction strategy to maximally exploit the dynamic workload variation is proposed for the offline voltage scheduling of preemptive systems. The idea is to construct a fully-preemptive schedule that leads to minimum energy consumption when the tasks take on approximately the average execution cycles yet still guarantees no deadline violation during the worst-case scenario. End-time for each sub-instance of the tasks obtained from the schedule is used for the on-line dynamic voltage scaling (DVS) of the tasks. For the tasks that normally require a small number of cycles but occasionally a large number of cycles to complete, such a schedule provides more opportunities for slack utilization and hence results in larger energy saving. The concept is realized by formulating the problem as a Non-Linear Programming (NLP) optimization problem. Experimental results show that, by using the proposed scheme, the total energy consumption at runtime is reduced by as high as 60% for randomly generated task sets when comparing with the static scheduling approach only using worst case workload.

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arXiv2007

Rapid Generation of Thermal-Safe Test Schedules

Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently been proposed to tackle this problem. However, as it will be shown in this paper, imposing a chip-level maximum power constraint doesn't necessarily avoid local overheating due to the non-uniform distribution of power across the chip. This paper proposes a new approach for dealing with overheating during test, by embedding thermal awareness into test scheduling. The proposed approach facilitates rapid generation of thermal-safer test schedules without requiring time-consuming thermal simulations. This is achieved by employing a low-complexity test session thermal model used to guide the test schedule generation algorithm. This approach reduces the chances of a design re-spin due to potential overheating during test.

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arXiv2007

System Synthesis for Networks of Programmable Blocks

The advent of sensor networks presents untapped opportunities for synthesis. We examine the problem of synthesis of behavioral specifications into networks of programmable sensor blocks. The particular behavioral specification we consider is an intuitive user-created network diagram of sensor blocks, each block having a pre-defined combinational or sequential behavior. We synthesize this specification to a new network that utilizes a minimum number of programmable blocks in place of the pre-defined blocks, thus reducing network size and hence network cost and power. We focus on the main task of this synthesis problem, namely partitioning pre-defined blocks onto a minimum number of programmable blocks, introducing the efficient but effective PareDown decomposition algorithm for the task. We describe the synthesis and simulation tools we developed. We provide results showing excellent network size reductions through such synthesis, and significant speedups of our algorithm over exhaustive search while obtaining near-optimal results for 15 real network designs as well as nearly 10,000 randomly generated designs.

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arXiv2007

Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems

As compared to a large spectrum of performance optimizations, relatively little effort has been dedicated to optimize other aspects of embedded applications such as memory space requirements, power, real-time predictability, and reliability. In particular, many modern embedded systems operate under tight memory space constraints. One way of satisfying these constraints is to compress executable code and data as much as possible. While research on code compression have studied efficient hardware and software based code strategies, many of these techniques do not take application behavior into account, that is, the same compression/decompression strategy is used irrespective of the application being optimized. This paper presents a code compression strategy based on control flow graph (CFG) representation of the embedded program. The idea is to start with a memory image wherein all basic blocks are compressed, and decompress only the blocks that are predicted to be needed in the near future. When the current access to a basic block is over, our approach also decides the point at which the block could be compressed. We propose several compression and decompression strategies that try to reduce memory requirements without excessively increasing the original instruction cycle counts.

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arXiv2007

Mutation Sampling Technique for the Generation of Structural Test Data

Our goal is to produce validation data that can be used as an efficient (pre) test set for structural stuck-at faults. In this paper, we detail an original test-oriented mutation sampling technique used for generating such data and we present a first evaluation on these validation data with regard to a structural test.

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arXiv2007

System Level Analysis of the Bluetooth Standard

The SystemC modules of the Link Manager Layer and Baseband Layer have been designed in this work at behavioral level to analyze the performances of the Bluetooth standard. In particular the probability of the creation of a piconet in presence of noise in the channel and the power reduction using the sniff and hold mode have been investigated.

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arXiv2007

LC Oscillator Driver for Safety Critical Applications

A CMOS harmonic signal LC oscillator driver for automotive applications working in a harsh environment with high safety critical requirements is described. The driver can be used with a wide range of external components parameters (LC resonance network of a sensor). Quality factor of the external LC network can vary two decades. Amplitude regulation of the driver is digitally controlled and the DAC is constructed as exponential with piece-wise-linear (PWL) approximation. Low current consumption for high quality resonance networks is achieved. Realized oscillator is robust, used in safety critical application and has low EMC emissions.

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arXiv2007

A CMOS-Based Tactile Sensor for Continuous Blood Pressure Monitoring

A monolithic integrated tactile sensor array is presented, which is used to perform non-invasive blood pressure monitoring of a patient. The advantage of this device compared to a hand cuff based approach is the capability of recording continuous blood pressure data. The capacitive, membrane-based sensor device is fabricated in an industrial CMOS-technology combined with post-CMOS micromachining. The capacitance change is detected by a S?-modulator. The modulator is operated at a sampling rate of 128kS/s and achieves a resolution of 12bit with an external decimation filter and an OSR of 128.

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arXiv2007

A Tool and Methodology for AC-Stability Analysis of Continuous-Time Closed-Loop Systems

Presented are a methodology and a DFII-based tool for AC-stability analysis of a wide variety of closed-loop continuous-time (operational amplifiers and other linear circuits). The methodology used allows for easy identification and diagnostics of ac-stability problems including not only main-loop effects but also local-instability loops in current mirrors, bias circuits and emitter or source followers without breaking the loop. The results of the analysis are easy to interpret. Estimated phase margin is readily available. Instability nodes and loops along with their respective oscillation frequencies are immediately identified and mapped to the existing circuit nodes thus offering significant advantages compared to traditional "black-box" methods of stability analysis (Transient Overshoot, Bode and Phase margin plots etc.). The tool for AC-Stability analysis is written in SKILL? and is fully integrated in DFII? environment. Its "push-button" graphical user interface (GUI) is easy to use and understand. The tool can be invoked directly from Composer? schematic and does not require active Analog Artist? session. The tool is not dependent on the use of a specific fabrication technology or Process Design Kit customization. It requires OCEAN?, Spectre? and Waveform calculator capabilities to run.

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arXiv2007

An Assembler Driven Verification Methodology (ADVM)

This paper presents an overview of an assembler driven verification methodology (ADVM) that was created and implemented for a chip card project at Infineon Technologies AG. The primary advantage of this methodology is that it enables rapid porting of directed tests to new targets and derivatives, with only a minimum amount of code refactoring. As a consequence, considerable verification development time and effort was saved.

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arXiv2007

Conception individuelle et collective. Approche de l'ergonomie cognitive [Individual and Collective Design. The Cognitive-Ergonomics Approach]

This text presents the cognitive-ergonomics approach to design, in both its individual and collective form. It focuses on collective design with respect to individual design. The theoretical framework adopted is that of information processing, specified for design problems. The cognitive characteristics of design problems are presented: the effects of their ill-defined character and of the different types of representation implemented in solving these problems, amongst others the more or less "satisficing" character of the different possible solutions. The text first describes the cognitive activities implemented in both individual and collective design: different types of control activities and of the executive activities of solution development and evaluation. Specific collective-design characteristics are then presented: co-design and distributed-design activities, temporo-operative and cognitive synchronisation, and different types of argumentation, of co-designers' intervention modes in the design process, of solution-proposals evaluation. The paper concludes by a confrontation between the two types of design, individual and collective.

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