arXiv2010
Time-to-market pressure and productivity gap force vendors and researchers to improve embedded system design methodology. Current used design method, Register Transfer Level (RTL), is no longer be adequate to comply with embedded system design necessity. It needs a new methodology for facing the lack of RTL. In this paper, a new methodology of hardware embedded system modeling process is designed for improving design process performance using Transaction Level Modeling (TLM). TLM is a higher abstraction design concept model above RTL model. Parameters measured include design process time and accuracy of design. For implementing RTL model used Avalon and Wishbone buses, both are System on Chip bus. Performance improvement measured by comparing TLM and RTL model process. The experiment results show performance improvements for Avalon RTL using new design methodology are 1,03 for 3-tiers, 1,47 for 4-tiers and 1,69 for 5-tiers. Performance improvements for Wishbone RTL are 1,12 for 3-tiers, 1,17 for 4-tiers and 1,34 for 5-tiers. These results show the trend of design process improvement.