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arXiv · 1104.1493

Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET

Tetsufumi Tanamoto·Hideyuki Sugiyama·Tomoaki Inokuchi·Takao Marukame·Mizue Ishikawa·Kazutaka Ikegami·Yoshiaki Saito
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Abstract

Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS FPGA for 22nm, 32nm and 45nm technologies including 20% transistor size variation. We show that area is reduced and speed is increased in spin FPGA owing to the nonvolatile memory function of spin MOSFET.

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Tetsufumi Tanamoto, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Kazutaka Ikegami, Yoshiaki Saito. 2011-04-08. Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET. https://doi.org/10.1063/1.3537923

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