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arXiv · 1405.7562

Dual Metal-Gate Planar Field-Effect Transistor for Electrostatically Doped CMOS Design

Tillmann Krauss·Frank Wessely·Udo Schwalke
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Abstract

In this paper, we demonstrate by simulation the general usability of an electrostatically doped and electrically reconfigurable planar field-effect transistor (FET) structure. The device concept is partly based on our already published and fabricated silicon nanowire 3D-FET technology. The technological key features of this general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate additionally enabling high-temperature operation of the proposed device. The transistors charge carrier type, i.e. n- or ptype FET, is electrically switchable on the fly by applying a control-gate voltage, which significantly increases the flexibility and versatility in digital integrated circuits.

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Tillmann Krauss, Frank Wessely, Udo Schwalke. 2014-05-29. Dual Metal-Gate Planar Field-Effect Transistor for Electrostatically Doped CMOS Design. https://arxiv.org/abs/1405.7562

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