arXiv subjects

Frank Wessely

Publications and source records attributed to Frank Wessely.

6 recordsLinked to original sources

arXiv2015

Novel Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications

In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our previously published Si-nanowire (SiNW) technology. Schottky barrier source/drain (S/D) contacts and a silicon-on-insulator (SOI) technology platform are the key features of this dual-gated but single channel universal FET. The combination of two electrically independent gates, one back-gate for S/D Schottky barrier modulation as well as channel formation to establish Schottky barrier FET (SBFET) operation and one front-gate forming a junctionless FET (JLFET) for actual current control, significantly increases the temperature robustness of the device.

cond-mat.mes-hall↗

arXiv2014

Dual Metal-Gate Planar Field-Effect Transistor for Electrostatically Doped CMOS Design

In this paper, we demonstrate by simulation the general usability of an electrostatically doped and electrically reconfigurable planar field-effect transistor (FET) structure. The device concept is partly based on our already published and fabricated silicon nanowire 3D-FET technology. The technological key features of this general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate additionally enabling high-temperature operation of the proposed device. The transistors charge carrier type, i.e. n- or ptype FET, is electrically switchable on the fly by applying a control-gate voltage, which significantly increases the flexibility and versatility in digital integrated circuits.

cond-mat.mtrl-sci↗

arXiv2014

Electrically Reconfigurable Dual Metal-Gate Planar Field-Effect Transistor for Dopant-free CMOS

In this paper, we demonstrate by simulation the feasibility of electrostatically doped and therefore reconfigurable planar field-effect-transistor (FET) structure which is based on our already fabricated and published Si-nanowire (SiNW) devices. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable on the fly by applying an appropriate control-gate voltage which significantly increases the versatility and flexibility in the design of digital integrated circuits.

cond-mat.mes-hall↗

arXiv2012

Transfer-free Grown Bilayer Graphene Transistors for Digital Applications

We invented a novel method to fabricate graphene transistors on oxidized silicon wafers without the need to transfer graphene layers. By means of catalytic chemical vapor deposition (CCVD) the in-situ grown bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate, whereby the number of stacked graphene layers is determined by the selected CCVD process parameters, e.g. temperature and gas mixture. BiLGFETs exhibit ultra-high on/off-current ratios of 107 at room temperature, exceeding previously reported values by several orders of magnitude. This will allow a simple and low-cost integration of graphene devices for digital nanoelectronic applications in a hybrid silicon CMOS environment for the first time.

cond-mat.mes-hall↗

arXiv2011

Transfer-free fabrication of graphene transistors

We invented a method to fabricate graphene transistors on oxidized silicon wafers without the need to transfer graphene layers. To stimulate the growth of graphene layers on oxidized silicon a catalyst system of nanometer thin aluminum/nickel double layer is used. This catalyst system is structured via liftoff before the wafer enters the catalytic chemical vapor deposition (CCVD) chamber. In the subsequent methane based growth process monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate, whereby the number of stacked graphene layers is determined by the selected CCVD process parameters, e.g. temperature and gas mixture. Subsequently, Raman spectroscopy is performed within the channel region in between the catalytic areas and the Raman spectra of fivelayer, bilayer and monolayer graphene confirm the existence of graphene grown by this silicon-compatible, transfer-free and in-situ fabrication approach. These graphene FETs will allow a simple and low-cost integration of graphene devices for nanoelectronic applications in a hybrid silicon CMOS environment.

cond-mat.mes-hall↗

arXiv2011

Silicon-CMOS Compatible In-Situ CCVD Grown Graphene Transistors with Ultra-High On/Off-Current Ratio

By means of catalytic chemical vapor deposition (CCVD) in-situ grown monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate without the need to transfer graphene layers. In-situ grown MoLGFETs exhibit the expected Dirac point together with the typical low on/off-current ratios. In contrast, BiLGFETs possess unipolar p-type device characteristics with an extremely high on/off-current ratio up to 1E7. The complete fabrication process is silicon CMOS compatible. This will allow a simple and low-cost integration of graphene devices for nanoelectronic applications in a hybrid silicon CMOS environment.

cond-mat.mes-hall↗