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arXiv · 1705.04991

Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing

Tsun-Ming Tseng·Bing Li·Ching-Feng Yeh·Hsiang-Chieh Jhan·Zuo-Ming Tsai·Mark Po-Hung Lin·Ulf Schlichtmann
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Abstract

With advancing process technologies and booming IoT markets, millimeter-wave CMOS RFICs have been widely developed in re- cent years. Since the performance of CMOS RFICs is very sensi- tive to the precision of the layout, precise placement of devices and precisely matched microstrip lengths to given values have been a labor-intensive and time-consuming task, and thus become a major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method to gener- ate high-quality RFIC layouts satisfying very stringent routing requirements of microstrip lines, including spacing/non-crossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both per- formance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout gener- ation time is significantly reduced from weeks to half an hour.

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Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Ming Tsai, Mark Po-Hung Lin, Ulf Schlichtmann. 2017-05-14. Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing. https://doi.org/10.1145/2897937.2898052

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