arXiv subjects

Tsun-Ming Tseng

Publications and source records attributed to Tsun-Ming Tseng.

5 recordsLinked to original sources

arXiv2026

Print-Aware Synthesis and Physical Design Methodologies for 3D-Printed Microfluidic Biochips

Microfluidic devices are widely used in diagnostics, chemical synthesis, and biological analysis, but their development often depends on complex fabrication and design processes. Resin-based three-dimensional (3D) printing has emerged as a promising alternative to conventional microfabrication because it enables low-cost, rapid prototyping of complex multi-layer structures. However, the practical realization of 3D-printed microfluidic biochips remains challenging due to manual and expertise-intensive design workflows, the rigid nature of commonly used printing materials, and fabrication inaccuracies such as over-curing that distort internal features and may block narrow channels. In this paper, we present a cohesive design automation framework for 3D-printed microfluidics that addresses these challenges across both device design and fabrication. The framework combines interactive design tools, automated synthesis methods for functional 3D microfluidic devices, techniques for developing low-cost 3D-printed mixers, and design-for-manufacturing strategies to improve print fidelity on low-cost resin printers.

cs.ET↗

arXiv2017

Post-Route Alleviation of Dense Meander Segments in High-Performance Printed Circuit Boards

Length-matching is an important technique to balance delays of bus signals in high-performance PCB routing. Existing routers, however, may generate dense meander segments with small distance. Signals propagating across these meander segments exhibit a speedup effect due to crosstalks between the segments of the same wire, thus leading to mismatch of arrival times even with the same physical wire length. In this paper, we propose a post-processing method to enlarge the width and the distance of meander segments and distribute them more evenly on the board so that the crosstalks can be reduced. In the proposed framework, we model the sharing combinations of available routing areas after removing dense meander segments from the initial routing, as well as the generation of relaxed meander segments and their groups in subareas. Thereafter, this model is transformed into an ILP problem and solved efficiently. Experimental results show that the proposed method can extend the width and the distance of meander segments about two times even under very tight area constraints, so that the crosstalks and thus the speedup effect can be alleviated effectively in high-performance PCB designs.

cs.AR↗

arXiv2017

Storage and Caching: Synthesis of Flow-based Microfluidic Biochips

Flow-based microfluidic biochips are widely used in lab- on-a-chip experiments. In these chips, devices such as mixers and detectors connected by micro-channels execute specific operations. Intermediate fluid samples are saved in storage temporarily until target devices become avail- able. However, if the storage unit does not have enough capacity, fluid samples must wait in devices, reducing their efficiency and thus increasing the overall execution time. Consequently, storage and caching of fluid samples in such microfluidic chips must be considered during synthesis to balance execution efficiency and chip area.

cs.ET↗

arXiv2017

ILP-based Alleviation of Dense Meander Segments with Prioritized Shifting and Progressive Fixing in PCB Routing

Length-matching is an important technique to bal- ance delays of bus signals in high-performance PCB routing. Existing routers, however, may generate very dense meander segments. Signals propagating along these meander segments exhibit a speedup effect due to crosstalk between the segments of the same wire, thus leading to mismatch of arrival times even under the same physical wire length. In this paper, we present a post-processing method to enlarge the width and the distance of meander segments and hence distribute them more evenly on the board so that crosstalk can be reduced. In the proposed framework, we model the sharing of available routing areas after removing dense meander segments from the initial routing, as well as the generation of relaxed meander segments and their groups for wire length compensation. This model is transformed into an ILP problem and solved for a balanced distribution of wire patterns. In addition, we adjust the locations of long wire segments according to wire priorities to swap free spaces toward critical wires that need much length compensation. To reduce the problem space of the ILP model, we also introduce a progressive fixing technique so that wire patterns are grown gradually from the edge of the routing toward the center area. Experimental results show that the proposed method can expand meander segments significantly even under very tight area constraints, so that the speedup effect can be alleviated effectively in high- performance PCB designs.

cs.AR↗

arXiv2017

Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing

With advancing process technologies and booming IoT markets, millimeter-wave CMOS RFICs have been widely developed in re- cent years. Since the performance of CMOS RFICs is very sensi- tive to the precision of the layout, precise placement of devices and precisely matched microstrip lengths to given values have been a labor-intensive and time-consuming task, and thus become a major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method to gener- ate high-quality RFIC layouts satisfying very stringent routing requirements of microstrip lines, including spacing/non-crossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both per- formance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout gener- ation time is significantly reduced from weeks to half an hour.

cs.ET↗