Post trimming of silicon photonics microresonators by nanoscale flash memory technology

Abstract

Flash memory technology is widely common in modern microelectronics, and is essentially affecting our daily life. Considering the recent progress in photonic circuitry, and in particular silicon photonics circuitry, there is now an opportunity to embed the flash memory technology in photonic applications. A particularly promising candidate that can benefit from such integration is the photonic resonator. As of today, chip scale resonators are essential building blocks in modern silicon photonic platform. However, their properties, and in particular their resonance frequencies deviate from their designed values due to unavoidable fabrication imperfections, imposing a stringent limitation on the applicability of such devices. Here we present a solution for this major obstacle and demonstrate electrical approach for post trimming of such resonators. This is achieved by integrating the well-established flash memory technology into the photonic circuitry. More specifically, we use the nanoscale Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) structure in order to trap charges in the thin silicon nitride layer, which is located in close proximity to the silicon device layer. This enables the accumulation of charges in the silicon, modifying the effective index of the optical mode and consequently the resonance frequency. By doing so, we provide a robust and elegant CMOS compatible memory solution, which can be easily manufactured and commercialized. We expect such an approach to pave the way for even more efficient utilization of resonators and interferometers in chip scale photonic and electro optic systems, with wide range of applications such as filters, modulators, sensors, and lasers, to name a few.