Chip-Level Electromigration Reliability Evaluation with Multiple On-Die Variation Effects

Karthik Airani; Rohit Guttal

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arXiv · 1712.05562

Chip-Level Electromigration Reliability Evaluation with Multiple On-Die Variation Effects

Karthik Airani·Rohit Guttal

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Abstract

In this paper, we briefly introduce physical foundations of electromigration (EM) and present a few classical EMrelated theories. We discuss physical parameters affecting EM wire lifetime and we introduce some background related to the existing EM physical simulators. In our work, for EM physical simulation we adopt the atomic concentration balance-based model. We discuss the simulation setup and results. We present a variation-aware electromigration (EM) analysis tool for power grid wires. The tool considers process variations caused by the chemical-mechanical polishing (CMP) and edge placement error (EPE). It uses a compact model that features critical region extraction and variation coefficient calculation.

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Karthik Airani, Rohit Guttal. 2017-12-15. Chip-Level Electromigration Reliability Evaluation with Multiple On-Die Variation Effects. https://arxiv.org/abs/1712.05562

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